-
公开(公告)号：US11095055B2
公开(公告)日：2021-08-17
申请号：US16742822
申请日：2020-01-14
Applicant: Raytheon Company
Inventor： Bradley S. Jaworski , Peter D. Morico
IPC: H01R9/24 , H01R13/514 , H01R13/58
Abstract: Systems and method are described for a terminal block that can include an insulating block that is composed of an electrically insulating material. The insulating structure can have a first via extending between a first and second opening in the insulating block. A second via can extend between a third and fourth opening in the insulating block. A distance between the first and second openings may be less than a distance between the third and fourth openings. A first electrical conducting element can extend between the first and second openings. A second electrical conducting element can extend between the third and fourth openings. The first and second electrical conducting elements can be separated from one another by a portion of the insulating block.
-
公开(公告)号：US20170221610A1
公开(公告)日：2017-08-03
申请号：US15013768
申请日：2016-02-02
Applicant: Raytheon Company
Inventor： Peter D. Morico , Bradley S. Jaworski
Abstract: A resistor includes a first resistor element. The first resistor element is connected to at least a first electrical terminal and a second electrical terminal. The first resistor element is configured to directly contact cooling media on at least two surfaces of the first resistor element in order to transfer heat away from the first resistor element. The resistor may also include a second resistor element connected to at least the first electrical terminal and the second electrical terminal, where the second resistor element is configured to directly contact the cooling media on at least two surfaces of the second resistor element in order to transfer heat away from the second resistor element.
-
公开(公告)号：US20170042027A1
公开(公告)日：2017-02-09
申请号：US15296198
申请日：2016-10-18
Applicant: RAYTHEON COMPANY
Inventor： Peter D. Morico , John D. Walker
CPC classification number: H05K1/142 , H05K1/0209 , H05K3/32 , H05K3/36 , H05K2201/066 , Y10T29/49126
Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
Abstract translation: 混合电路组件包括其上安装有高电压，大功率部件的集成金属基板（IMS）。 IMS在金属基板上包括金属基板和绝缘粘合剂，以及绝缘粘合剂上的一个或多个布线层。 混合电路组件包括其上安装有低电压，低功率元件的多层印刷电路板（PWB）。 多层PWB连接到IMS并具有与IMS的上表面共面的上表面。 PWB通过绝缘粘合剂安装在金属基板上。
-
Patent Agency Ranking
公开(公告)号：US09504157B2
公开(公告)日：2016-11-22
申请号：US14016806
申请日：2013-09-03
Applicant: RAYTHEON COMPANY
Inventor： Peter D. Morico , John D. Walker
CPC classification number: H05K1/142 , H05K1/0209 , H05K3/32 , H05K3/36 , H05K2201/066 , Y10T29/49126
Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
Abstract translation: 混合电路组件包括其上安装有高电压，大功率部件的集成金属基板（IMS）。 IMS在金属基板上包括金属基板和绝缘粘合剂，以及绝缘粘合剂上的一个或多个布线层。 混合电路组件包括其上安装有低电压，低功率元件的多层印刷电路板（PWB）。 多层PWB连接到IMS并具有与IMS的上表面共面的上表面。 PWB通过绝缘粘合剂安装在金属基板上。
-
公开(公告)号：US20210226357A1
公开(公告)日：2021-07-22
申请号：US16742822
申请日：2020-01-14
Applicant: Raytheon Company
Inventor： Bradley S. Jaworski , Peter D. Morico
Abstract: Systems and method are described for a terminal block that can include an insulating block that is composed of an electrically insulating material. The insulating structure can have a first via extending between a first and second opening in the insulating block. A second via can extend between a third and fourth opening in the insulating block. A distance between the first and second openings may be less than a distance between the third and fourth openings. A first electrical conducting element can extend between the first and second openings. A second electrical conducting element can extend between the third and fourth openings. The first and second electrical conducting elements can be separated from one another by a portion of the insulating block.
-
公开(公告)号：US20150062855A1
公开(公告)日：2015-03-05
申请号：US14016806
申请日：2013-09-03
Applicant: RAYTHEON COMPANY
Inventor： Peter D. Morico , John D. Walker
CPC classification number: H05K1/142 , H05K1/0209 , H05K3/32 , H05K3/36 , H05K2201/066 , Y10T29/49126
Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
Abstract translation: 混合电路组件包括其上安装有高电压，大功率部件的集成金属基板（IMS）。 IMS在金属基板上包括金属基板和绝缘粘合剂，以及绝缘粘合剂上的一个或多个布线层。 混合电路组件包括其上安装有低电压，低功率元件的多层印刷电路板（PWB）。 多层PWB连接到IMS并具有与IMS的上表面共面的上表面。 PWB通过绝缘粘合剂安装在金属基板上。
-
公开(公告)号：US10219375B2
公开(公告)日：2019-02-26
申请号：US15296198
申请日：2016-10-18
Applicant: RAYTHEON COMPANY
Inventor： Peter D. Morico , John D. Walker
Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
-
公开(公告)号：US09941036B2
公开(公告)日：2018-04-10
申请号：US15013768
申请日：2016-02-02
Applicant: Raytheon Company
Inventor： Peter D. Morico , Bradley S. Jaworski
Abstract: A resistor includes a first resistor element. The first resistor element is connected to at least a first electrical terminal and a second electrical terminal. The first resistor element is configured to directly contact cooling media on at least two surfaces of the first resistor element in order to transfer heat away from the first resistor element. The resistor may also include a second resistor element connected to at least the first electrical terminal and the second electrical terminal, where the second resistor element is configured to directly contact the cooling media on at least two surfaces of the second resistor element in order to transfer heat away from the second resistor element.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.011 seconds)
