公开(公告)号：US20220285298A1

公开(公告)日：2022-09-08

申请号：US17190850

申请日：2021-03-03

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  Chad Fulk ,  Aaron M. Ramirez

IPC: H01L23/00 ,  H01L31/02 ,  H01L31/0216 ,  H01L25/16

Abstract: An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

公开(公告)号：US12002773B2

公开(公告)日：2024-06-04

申请号：US17190850

申请日：2021-03-03

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  Chad Fulk ,  Aaron M. Ramirez

IPC: H01L25/16 ,  H01L23/00 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0296 ,  H01L31/09

CPC classification number: H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L25/167 ,  H01L31/02002 ,  H01L31/0216 ,  H01L24/03 ,  H01L24/27 ,  H01L24/83 ,  H01L31/0224 ,  H01L31/02966 ,  H01L31/09 ,  H01L2224/03845 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05564 ,  H01L2224/05609 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/2783 ,  H01L2224/29026 ,  H01L2224/29034 ,  H01L2224/29188 ,  H01L2224/32145 ,  H01L2224/80815 ,  H01L2224/83896 ,  H01L2924/3512

Abstract: An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

公开(公告)号：US20220416095A1

公开(公告)日：2022-12-29

申请号：US17361859

申请日：2021-06-29

Applicant: Raytheon Company

Inventor： Chad Fulk ,  Sean P. Kilcoyne ,  Stuart Farrell ,  Eric Miller ,  Andrew Clarke

IPC: H01L31/02 ,  H01L21/768 ,  H01L31/18 ,  H01L31/103 ,  H01L21/02

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.