公开(公告)号：US20220115423A1

公开(公告)日：2022-04-14

申请号：US17068223

申请日：2020-10-12

Applicant: Raytheon Company

Inventor： Eric Miller ,  Christian M. Boemler ,  Justin Gordon Adams Wehner ,  Drew Fairbanks ,  Sean P. Kilcoyne

IPC: H01L27/146 ,  H01L27/148 ,  H04N5/378

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

公开(公告)号：US20200273893A1

公开(公告)日：2020-08-27

申请号：US16285690

申请日：2019-02-26

Applicant: Raytheon Company

Inventor： Jeffery H. Burkhart ,  Sean P. Kilcoyne ,  Eric Miller

IPC: H01L27/146 ,  H01L23/00

Abstract: Methods and apparatus for proving a sensor assembly. Embodiments can include employing a circuit assembly having a first layer bonded to a second layer with an oxide layer, depositing bonding oxide on the second layer of the circuit assembly, and thinning the first layer of the circuit assembly after depositing the bonding oxide. A coating can be applied over at least a portion of the first layer of the circuit assembly after annealing the circuit assembly. After polishing the bonding oxide on the second surface of the second layer of the circuit assembly, a shim can be secured to the bonding oxide on the second surface of the second layer of the circuit assembly to reduce bow of the assembly. Embodiments can provide a sensor useful in focal plane arrays.

公开(公告)号：US20220310690A1

公开(公告)日：2022-09-29

申请号：US17212085

申请日：2021-03-25

Applicant: Raytheon Company

Inventor： David J. Gulbransen ,  Sean P. Kilcoyne ,  Eric Miller ,  Matthew D. Chambers ,  Eric J. Beuville ,  Andrew E. Gin ,  Adam M. Kennedy

IPC: H01L27/146 ,  H01L21/66 ,  H01L23/00

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

公开(公告)号：US20210043665A1

公开(公告)日：2021-02-11

申请号：US17074736

申请日：2020-10-20

Applicant: Raytheon Company

Inventor： Jeffery H. Burkhart ,  Sean P. Kilcoyne ,  Eric Miller

IPC: H01L27/146 ,  H01L23/00

Abstract: An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.

公开(公告)号：US20240055466A1

公开(公告)日：2024-02-15

申请号：US18494163

申请日：2023-10-25

Applicant: Raytheon Company

Inventor： Eric Miller ,  Christian M. Boemler ,  Justin Gordon Adams Wehner ,  Drew Fairbanks ,  Sean P. Kilcoyne

IPC: H01L27/146 ,  H01L27/148 ,  H01L23/498 ,  H01L21/311 ,  H01L23/488 ,  H01L23/48 ,  H01L23/485 ,  H04N25/75

CPC classification number: H01L27/1469 ,  H01L27/14685 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/148 ,  H01L23/49827 ,  H01L21/311 ,  H01L27/1462 ,  H01L23/488 ,  H01L23/481 ,  H01L27/14632 ,  H01L23/485 ,  H04N25/75

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

公开(公告)号：US11837623B2

公开(公告)日：2023-12-05

申请号：US17068223

申请日：2020-10-12

Applicant: Raytheon Company

Inventor： Eric Miller ,  Christian M. Boemler ,  Justin Gordon Adams Wehner ,  Drew Fairbanks ,  Sean P. Kilcoyne

IPC: H01L27/146 ,  H01L27/148 ,  H01L23/498 ,  H01L21/311 ,  H01L23/488 ,  H01L23/48 ,  H01L23/485 ,  H04N25/75

CPC classification number: H01L27/1469 ,  H01L21/311 ,  H01L23/481 ,  H01L23/485 ,  H01L23/488 ,  H01L23/49827 ,  H01L27/148 ,  H01L27/1462 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H04N25/75

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

公开(公告)号：US20220416095A1

公开(公告)日：2022-12-29

申请号：US17361859

申请日：2021-06-29

Applicant: Raytheon Company

Inventor： Chad Fulk ,  Sean P. Kilcoyne ,  Stuart Farrell ,  Eric Miller ,  Andrew Clarke

IPC: H01L31/02 ,  H01L21/768 ,  H01L31/18 ,  H01L31/103 ,  H01L21/02

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

公开(公告)号：US12261186B2

公开(公告)日：2025-03-25

申请号：US17212085

申请日：2021-03-25

Applicant: Raytheon Company

Inventor： David J. Gulbransen ,  Sean P. Kilcoyne ,  Eric Miller ,  Matthew D. Chambers ,  Eric J. Beuville ,  Andrew E. Gin ,  Adam M. Kennedy

IPC: H01L25/00 ,  H01L21/66 ,  H01L23/00 ,  H01L27/146

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.