公开(公告)号：US11894477B2

公开(公告)日：2024-02-06

申请号：US17322073

申请日：2021-05-17

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  Emily Thomson ,  Michael Rondon

IPC: H01L27/146 ,  H01L31/0392 ,  H01L31/0296 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/03925 ,  H01L27/1465 ,  H01L27/1469 ,  H01L31/02966 ,  H01L31/1032 ,  H01L31/1832

Abstract: An electrical device includes a substrate with a compressive layer, a neutral stress buffer layer and a tensile stress compensation layer. The stress buffer layer and the stress compensation layer may each be formed with aluminum nitride using different processing parameters to provide a different intrinsic stress value for each layer. The aluminum nitride tensile layer is configured to counteract stresses from the compressive layer in the device to thereby control an amount of substrate bow in the device. This is useful for protecting fragile materials in the device, such as mercury cadmium telluride. The aluminum nitride stress compensation layer also can compensate for forces, such as due to CTE mismatches, to protect the fragile layer. The device may include temperature-sensitive materials, and the aluminum nitride stress compensation layer or stress buffer layer may be formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

公开(公告)号：US11854879B2

公开(公告)日：2023-12-26

申请号：US17184756

申请日：2021-02-25

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  John J. Drab ,  Faye Walker

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76886 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53233

Abstract: A Cu3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

公开(公告)号：US20230082114A1

公开(公告)日：2023-03-16

申请号：US17475962

申请日：2021-09-15

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  David R. Rhiger ,  Chad W. Fulk ,  Stuart B. Farrell ,  James Pattison ,  Jeffrey M. Peterson ,  Chad M. Althouse

IPC: H01L31/18 ,  H01L31/0296 ,  H01L31/0224

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

公开(公告)号：US20220285298A1

公开(公告)日：2022-09-08

申请号：US17190850

申请日：2021-03-03

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  Chad Fulk ,  Aaron M. Ramirez

IPC: H01L23/00 ,  H01L31/02 ,  H01L31/0216 ,  H01L25/16

Abstract: An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

公开(公告)号：US20210136915A1

公开(公告)日：2021-05-06

申请号：US16671468

申请日：2019-11-01

Applicant: Raytheon Company

Inventor： Christine Frandsen ,  John J. Drab ,  Andrew Clarke

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/40 ,  H01L21/48 ,  H05K1/03 ,  H01L23/498

Abstract: A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.

公开(公告)号：US11851785B2

公开(公告)日：2023-12-26

申请号：US17326615

申请日：2021-05-21

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  David R. Rhiger ,  George Grama ,  Stuart B. Farrell

IPC: H01L31/18 ,  C30B25/18 ,  C30B29/40 ,  C30B29/60

CPC classification number: C30B25/183 ,  C30B29/403 ,  C30B29/605 ,  H01L31/1832 ,  H01L31/1868

Abstract: An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg1-xCdxTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

公开(公告)号：US20220293661A1

公开(公告)日：2022-09-15

申请号：US17686692

申请日：2022-03-04

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  James Pattison ,  Stuart Farrell

IPC: H01L27/146

Abstract: An electrical device including a substrate, a dielectric layer supported by the substrate having at least one vertical post disposed within a via hole of the dielectric layer, and at least one electrically conductive vertical interconnect laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non-tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

公开(公告)号：US12002773B2

公开(公告)日：2024-06-04

申请号：US17190850

申请日：2021-03-03

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  Chad Fulk ,  Aaron M. Ramirez

IPC: H01L25/16 ,  H01L23/00 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0296 ,  H01L31/09

CPC classification number: H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L25/167 ,  H01L31/02002 ,  H01L31/0216 ,  H01L24/03 ,  H01L24/27 ,  H01L24/83 ,  H01L31/0224 ,  H01L31/02966 ,  H01L31/09 ,  H01L2224/03845 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05564 ,  H01L2224/05609 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/2783 ,  H01L2224/29026 ,  H01L2224/29034 ,  H01L2224/29188 ,  H01L2224/32145 ,  H01L2224/80815 ,  H01L2224/83896 ,  H01L2924/3512

Abstract: An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

公开(公告)号：US11817521B2

公开(公告)日：2023-11-14

申请号：US17475962

申请日：2021-09-15

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  David R. Rhiger ,  Chad W. Fulk ,  Stuart B. Farrell ,  James Pattison ,  Jeffrey M. Peterson ,  Chad M. Althouse

IPC: H01L31/18 ,  H01L31/0224 ,  H01L31/0296

CPC classification number: H01L31/1832 ,  H01L31/02966 ,  H01L31/022408 ,  H01L31/1864

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

公开(公告)号：US11659660B2

公开(公告)日：2023-05-23

申请号：US16671468

申请日：2019-11-01

Applicant: Raytheon Company

Inventor： Christine Frandsen ,  John J. Drab ,  Andrew Clarke

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/4623

Abstract: A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.