公开(公告)号：US20150061400A1

公开(公告)日：2015-03-05

申请号：US14332082

申请日：2014-07-15

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： No Il PARK ,  Seung Wook PARK ,  Chang Bae LEE ,  Chang Ryul JUNG

IPC: H01F38/14 ,  H02J7/02 ,  H01F41/04 ,  H01F27/28

CPC classification number: H01F38/14 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/041 ,  H02J7/025 ,  H02J50/10 ,  H04B5/0037 ,  H04B5/0075 ,  Y10T29/4902

Abstract: The present invention relates to a coil type unit for wireless power transmission, a wireless power transmission device, an electronic device, and a manufacturing method of a coil type unit for wireless power transmission. A coil type unit for wireless power transmission of the present invention includes a coil portion having a coil pattern on a substrate; a magnetic portion having the coil portion attached to one surface thereof and a conductive pattern formed thereon; an adhesive portion interposed between the magnetic portion and the coil portion to mutually bond the magnetic portion and the coil portion; and a conductive hole for electrically connecting the coil pattern and the conductive pattern, wherein the adhesive portion is formed on one surface of the magnetic portion having the conductive pattern thereon while being formed in an area other than the area in which the conductive pattern is formed.

Abstract translation: 本发明涉及一种用于无线电力传输的线圈类型单元，无线电力传输装置，电子设备以及用于无线电力传输的线圈型单元的制造方法。 本发明的无线电力传输线圈型单元包括在基板上具有线圈图案的线圈部分; 具有安装在其一个表面上的线圈部分和形成在其上的导电图案的磁性部分; 插入在所述磁性部分和所述线圈部分之间以将所述磁性部分和所述线圈部分相互粘合的粘合部分; 以及用于电连接线圈图案和导电图案的导电孔，其中粘合部分形成在具有导电图案的磁性部分的一个表面上，同时形成在除了形成导电图案的区域之外的区域中 。

公开(公告)号：US20150055312A1

公开(公告)日：2015-02-26

申请号：US14250965

申请日：2014-04-11

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jeong Ho LEE ,  Mi Jin PARK ,  Chang Bae LEE ,  Young Do KWEON

IPC: H05K1/11 ,  H05K13/04 ,  H05K3/10 ,  B23K1/00 ,  H05K1/18 ,  H05K3/18

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/041

Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.

Abstract translation: 本发明公开了一种内插衬底，包括：穿透核心层的核心层和穿芯通孔（TCV）; 形成在芯层的两个表面上的电路布线和TCV上焊盘和TCV下焊盘，其各自结合到形成在芯层的两个表面上的TCV的上表面和下表面; 覆盖TCV上焊盘的上绝缘层和形成在芯层的一个表面上并且在其上表面上形成电路布线的电路布线; 通过穿过每层的上绝缘层并且具有连接到TCV上垫的一端的叠层; 以及覆盖TCV下焊盘的下绝缘层和形成在芯层的另一表面上的电路布线，并且设置有暴露TCV下焊盘的开口。

公开(公告)号：US20170061189A1

公开(公告)日：2017-03-02

申请号：US15093997

申请日：2016-04-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Il KWON ,  Chang Bae LEE ,  Hyun Jun KIM ,  Young Ki LEE

IPC: G06K9/00

CPC classification number: G06K9/0002

Abstract: Disclosed are sensors for detecting a fingerprint and methods of manufacturing the sensor. The sensor for detecting a fingerprint includes a substrate, first conductor lines formed on a surface of the substrate, an insulating layer formed on the first conductor lines, and second conductor lines formed on the insulating layer. A width of the first conductor lines or a width of the second conductor lines is 1-10 μm.

Abstract translation: 公开了用于检测指纹的传感器和制造传感器的方法。 用于检测指纹的传感器包括基板，形成在基板的表面上的第一导体线，形成在第一导体线上的绝缘层，以及形成在绝缘层上的第二导体线。 第一导体线的宽度或第二导体线的宽度为1-10μm。

公开(公告)号：US20190019757A1

公开(公告)日：2019-01-17

申请号：US15819541

申请日：2017-11-21

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ji Hyun LEE ,  Jin Gu KIM ,  Chang Bae LEE ,  Jin Su KIM

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.

公开(公告)号：US20170373029A1

公开(公告)日：2017-12-28

申请号：US15471205

申请日：2017-03-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Jin SEOL ,  Chang Bae LEE ,  Min Seok JANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/25 ,  H01L29/0657 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16238 ,  H01L2224/18 ,  H01L2224/20 ,  H01L2224/221 ,  H01L2224/24155 ,  H01L2224/244 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2924/10156 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15153

Abstract: A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least some portions of the first interconnection member and the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the semiconductor chip. The first interconnection member and the second interconnection member respectively include a plurality of redistribution layers electrically connected to the connection pads of the semiconductor chip, and the semiconductor chip has a groove defined in the active surface and between a peripheral edge of the semiconductor chip and the connection pads of the semiconductor chip.

公开(公告)号：US20160143137A1

公开(公告)日：2016-05-19

申请号：US14878496

申请日：2015-10-08

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Yong Ho BAEK ,  Jung Hyun CHO ,  Young Gwan KO ,  Chang Bae LEE

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/10 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/4694 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K3/4682 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: There are provided a printed circuit board, a method of manufacturing the same, and an electronic component module. The printed circuit board comprises a first circuit layer; a first insulating layer formed to cover a portion or all of the first circuit layer; a second circuit layer formed on the first insulating layer; a second insulating layer formed on an overall surface of the board so as to cover the first circuit layer and the second circuit layer; and a third circuit layer formed in the second insulating layer. The second circuit layer has a circuit pattern of a fine pitch as compared to the first circuit layer and the third circuit layer.

Abstract translation: 提供了印刷电路板，其制造方法和电子部件模块。 印刷电路板包括第一电路层; 形成为覆盖所述第一电路层的一部分或全部的第一绝缘层; 形成在所述第一绝缘层上的第二电路层; 形成在所述基板的整个表面上以覆盖所述第一电路层和所述第二电路层的第二绝缘层; 以及形成在所述第二绝缘层中的第三电路层。 与第一电路层和第三电路层相比，第二电路层具有精细间距的电路图案。

公开(公告)号：US20150334832A1

公开(公告)日：2015-11-19

申请号：US14598595

申请日：2015-01-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Min BAEK ,  Yoon Su KIM ,  Jin Hyuck YANG ,  Chang Bae LEE

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/40

CPC classification number: H05K1/111 ,  H05K3/108 ,  H05K3/188 ,  H05K3/388 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/09381 ,  H05K2203/0713 ,  H05K2203/0716 ,  H05K2203/0723 ,  H05K2203/1407 ,  Y10T428/12396

Abstract: The present invention relates to an electrode structure which includes: a base substrate; a seed layer provided on one or both surfaces of the base substrate; an electroplating layer provided on the seed layer; and barriers discontinuously provided between the seed layer and the electroplating layer.

Abstract translation: 本发明涉及电极结构，其包括：基底; 种子层，设置在所述基底基板的一个或两个表面上; 设置在种子层上的电镀层; 并且在种子层和电镀层之间不连续地提供阻挡层。

公开(公告)号：US20150000958A1

公开(公告)日：2015-01-01

申请号：US14074338

申请日：2013-11-07

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyoung Moo HARR ,  Hyung Jin JEON ,  Jin Gu KIM ,  Young Jae LEE ,  Young Do KWEON ,  Chang Bae LEE

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4647 ,  H05K2201/09827

Abstract: The present invention discloses a printed circuit board including a lower wiring layer, an insulating layer which buries the lower wiring layer, and an upper wiring layer formed on the insulating layer to improve reliability of interlayer electrical connection between the wiring layers, wherein the interlayer connection between the upper wiring layer and the lower wiring layer is performed by a via electrode which is provided between the upper wiring layer and the lower wiring layer and has an upper surface bonded to the upper wiring layer and a lower surface bonded to the lower wiring layer, wherein the lower surface of the via electrode is larger than the upper surface thereof.

Abstract translation: 本发明公开了一种印刷电路板，包括下布线层，埋置下布线层的绝缘层和形成在绝缘层上的上布线层，以提高布线层之间的层间电连接的可靠性，其中层间连接 上布线层和下布线层之间的通孔电极通过设置在上布线层和下布线层之间的通孔电极进行，并且具有与上布线层接合的上表面和接合到下布线层的下表面 其中，所述通孔电极的下表面大于其上表面。

公开(公告)号：US20140182905A1

公开(公告)日：2014-07-03

申请号：US14143475

申请日：2013-12-30

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyung Moo HAR ,  Chang Bae LEE ,  Jin Gu KIM ,  Young Do KWEON

IPC: H05K13/00 ,  H05K1/09

CPC classification number: H05K1/09 ,  H05K3/247 ,  H05K3/3484 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/081

Abstract: Disclosed herein are a printed circuit board including a copper foil layer surface treated with Pb-free solder having the same height as that of a solder resist, and a surface treatment method of the printed circuit board.According to the present invention, the surface treatment of the package board or interposer board having an ultra-fine pitch (300 μm or less) may be easily implemented by a cheap process. In addition, the surface treatment of the printed circuit board may be eco-friendly performed by using the Pb-free solder, and it may be easy to surface treat the package board or interposer board based on the organic material sensitive to a high temperature.

Abstract translation: 本发明公开了一种印刷电路板，其包括利用与阻焊剂相同高度的无铅焊料处理的铜箔层表面和印刷电路板的表面处理方法。 根据本发明，可以通过廉价的处理容易地实现具有超细间距（300μm以下）的封装基板或中介板的表面处理。 此外，印刷电路板的表面处理可以通过使用无铅焊料进行环保处理，并且可以容易地基于对高温敏感的有机材料来表面处理封装板或插入板。

公开(公告)号：US20130320561A1

公开(公告)日：2013-12-05

申请号：US13906951

申请日：2013-05-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Wook PARK ,  Romero CHRISTIAN ,  Chang Bae LEE ,  Mi Jin PARK

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76877 ,  H01L2924/0002 ,  H05K1/112 ,  H05K1/113 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09481 ,  H05K2201/0959 ,  H01L2924/00

Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t′ formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness α from a top of the circuit pattern, wherein T≦t″+α is satisfied, T represents a sum of the thicknesses t and t′ and t″ is a thickness of a portion of the circuit pattern formed on the via plug.

Abstract translation: 本文公开了一种插头通孔堆叠结构，包括：镀敷在通孔内壁上且贯穿孔的顶部和底部的通孔镀层，厚度为t; 通孔塞，其填充在所述通孔镀层的内部空间中; 形成在通孔镀层和通孔塞的顶部和底部上并形成在厚度t以上的通孔镀层上的厚度t'的电路图案; 以及填充在通孔顶部形成的通孔的叠层导电通孔，其形成为从电路图案的顶部的厚度α，其中T @ t“+α满足，T表示厚度t的和 并且t'和t“是形成在通孔塞上的电路图案的一部分的厚度。