公开(公告)号：US20140281656A1

公开(公告)日：2014-09-18

申请号：US13798604

申请日：2013-03-13

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Rodney A. Ruesch ,  Eric C. Fromm ,  Robert W. Cutler ,  Richard G. Finstad ,  Dale R. Purdy ,  Brian J. Johnson ,  John F. Steiner

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H04J3/0638 ,  H04J3/0661

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract translation: 为HPC系统中的每个处理器生成处理器时钟信号，使得所有处理器时钟信号具有相同的频率。 此外，作为启动（启动）过程的一部分，进程设置处理器的所有时间戳计数器（TSC），这样它们表示相同的时间。 HPC系统的每个刀片从同步通信网络恢复恢复的时钟信号，刀片耦合到同步通信网络。 刀片从恢复的时钟信号产生处理器时钟，并将处理器时钟提供给刀片上的处理器。 每个机箱耦合到第二个系统级的同步通信网络，每个机箱将其机箱同步通信网络与全系统的同步通信系统同步。 因此，所有处理器时钟信号都以相同的频率生成。

公开(公告)号：US20140281266A1

公开(公告)日：2014-09-18

申请号：US13804537

申请日：2013-03-14

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Brian J. Johnson

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0806 ,  G06F12/0815 ,  G06F2212/1032

Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.

Abstract translation: 公开了一种高性能计算系统和方法。 该系统包括具有物理可移动节点的逻辑分区，每个节点具有至少一个处理器，以及可以与其他节点共享的存储器。 可以将节点硬件删除或分配给另一个分区，而无需重新启动或重新启动电源。 使用内存目录跟踪内存共享。 内存目录中的缓存一致性操作包括一个测试，以确定给定的远程节点是否已被删除。 如果远程节点不存在，则系统硬件模拟来自丢失节点的有效响应。

公开(公告)号：US09632934B2

公开(公告)日：2017-04-25

申请号：US13804537

申请日：2013-03-14

Applicant: Silicon Graphics International Corp.

Inventor： Brian J. Johnson

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0815 ,  G06F12/0806

CPC classification number: G06F12/0817 ,  G06F12/0806 ,  G06F12/0815 ,  G06F2212/1032

Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.

公开(公告)号：US09104343B2

公开(公告)日：2015-08-11

申请号：US13798604

申请日：2013-03-13

Applicant: Silicon Graphics International Corp.

Inventor： Rodney A. Ruesch ,  Eric C. Fromm ,  Robert W. Cutler ,  Richard G. Finstad ,  Dale R. Purdy ,  Brian J. Johnson ,  John F. Steiner

IPC: G06F1/08 ,  H04J3/06

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H04J3/0638 ,  H04J3/0661

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract translation: 为HPC系统中的每个处理器生成处理器时钟信号，使得所有处理器时钟信号具有相同的频率。 此外，作为启动（启动）过程的一部分，进程设置处理器的所有时间戳计数器（TSC），这样它们表示相同的时间。 HPC系统的每个刀片从同步通信网络恢复恢复的时钟信号，刀片耦合到同步通信网络。 刀片从恢复的时钟信号产生处理器时钟，并将处理器时钟提供给刀片上的处理器。 每个机箱耦合到第二个系统级的同步通信网络，每个机箱将其机箱同步通信网络与全系统的同步通信系统同步。 因此，所有处理器时钟信号都以相同的频率生成。