公开(公告)号：US11687420B2

公开(公告)日：2023-06-27

申请号：US17563641

申请日：2021-12-28

Applicant: SK hynix Inc.

Inventor： Wen Jyh Lin ,  Yun Chih Huang ,  Fu Hsiung Lin

IPC: G06F11/20

CPC classification number: G06F11/2005 ,  G06F11/201 ,  G06F2201/85

Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

公开(公告)号：US12170128B2

公开(公告)日：2024-12-17

申请号：US17869429

申请日：2022-07-20

Applicant: SK hynix Inc.

Inventor： Fu Hsiung Lin

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.

公开(公告)号：US12045179B2

公开(公告)日：2024-07-23

申请号：US18116177

申请日：2023-03-01

Applicant: SK hynix Inc.

Inventor： Fu Hsiung Lin ,  Lan Feng Wang

IPC: G06F13/10 ,  G06F9/4401 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/1668 ,  G06F9/4418 ,  G06F13/382

Abstract: A method for handling configuration data for an interconnection protocol within hibernation operation, a controller and an electronic device are provided. The method includes the following steps. In an electronic device, a hibernation entering indication signal indicating entering a hibernation state of the interconnection protocol is received. The electronic device has a memory and an index table, wherein the index table includes attribute identifiers corresponding to management information base (MIB) attributes, which belong to sub-layers of a link layer of the interconnection protocol and are required to be retained during hibernation. In response to the hibernation entering indication signal, MIB attribute storing is performed by a hardware protocol engine for implementing the link layer to read, for each one of the sub-layers, attribute data from the sub-layers according to the attribute identifiers from the index table sequentially and to write the attribute data sequentially to the memory. After the entering the hibernation state, the hardware protocol engine is in a power saving state or off while the memory remains on.

公开(公告)号：US11892927B2

公开(公告)日：2024-02-06

申请号：US17562729

申请日：2021-12-27

Applicant: SK hynix Inc.

Inventor： Fu Hsiung Lin

IPC: G06F11/00 ,  G06F11/30 ,  G06F13/38 ,  G06F11/07 ,  H04L1/00

CPC classification number: G06F11/3041 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/3034 ,  G06F13/382 ,  H04L1/0083

Abstract: A method for error handling of an interconnection protocol, a controller, and a storage device are provided. The method includes receiving a frame error position indication signal to indicate whether an error occurs in a frame in each clock cycle and a symbol position corresponding to the error, and receiving a frame correction position indication signal to indicate whether the frame in each clock cycle is correct and a symbol position corresponding to the frame that is correct; according to the frame error position indication signal and the frame correction position indication signal, determining that a frame error occurs in a first clock cycle, and after requesting for NAC frame transmission, sending a request for disabling the NAC frame transmission; and after the first clock cycle, comparing the frame error position indication signal and the frame correction position indication signal.

公开(公告)号：US11811897B2

公开(公告)日：2023-11-07

申请号：US17562701

申请日：2021-12-27

Applicant: SK hynix Inc.

Inventor： Fu Hsiung Lin

IPC: H04L69/00 ,  H04L69/324 ,  G06F13/42

CPC classification number: H04L69/02 ,  G06F13/4282 ,  H04L69/324

Abstract: A method for data processing of frame receiving of an interconnection protocol and a storage device, for use in a first device linkable to a second device according to the interconnection protocol. The method includes: in processing of frames originating from the second device and received by the first device: while sending data contained in a first frame to a network layer from a data link layer, pre-fetching symbols of a second frame; and after the data contained in the first frame are sent to the network layer and the symbols of the second frame are pre-fetched, sending data contained in the second frame to the network layer. Upon receipt of back-to-back frames, the efficiency of the frame receiving at the data link layer is enhanced.