公开(公告)号：US11687420B2

公开(公告)日：2023-06-27

申请号：US17563641

申请日：2021-12-28

Applicant: SK hynix Inc.

Inventor： Wen Jyh Lin ,  Yun Chih Huang ,  Fu Hsiung Lin

IPC: G06F11/20

CPC classification number: G06F11/2005 ,  G06F11/201 ,  G06F2201/85

Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

公开(公告)号：US11782636B2

公开(公告)日：2023-10-10

申请号：US17559438

申请日：2021-12-22

Applicant: SK hynix Inc.

Inventor： Wen Jyh Lin

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/38 ,  G06F13/14

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/14 ,  G06F13/387 ,  G06F13/42

Abstract: A method for data processing of an interconnection protocol, a controller and a storage device, the method comprising in processing of frame sending by a first device to a second device: allocating a plurality of start-of-frame (SOF)-included protocol data units (PDUs) to a designated lane among a plurality of active lanes of the first device; and configuring a PDU distance among the plurality of start-of-frame (SOF)-included protocol data units to be greater than or equal to a product of a maximum bus width of a lane of the interconnection protocol and a quantity of the plurality of active lanes. Accordingly, the method can help greatly reduce the complexity of the hardware protocol engine implemented under the interconnection protocol, especially the complexity of the decoder in the data link layer receiver, thus reducing the difficulty of research and development, verification and maintenance.

公开(公告)号：US11716169B2

公开(公告)日：2023-08-01

申请号：US17684080

申请日：2022-03-01

Applicant: SK hynix Inc.

Inventor： Cheng Wei Yu ,  Wen Jyh Lin ,  Lan Feng Wang

IPC: H04L1/00 ,  H04L67/1097

CPC classification number: H04L1/0046 ,  H04L1/0041 ,  H04L1/0067 ,  H04L67/1097

Abstract: A method for error handling of an interconnection protocol, a controller and a storage device are provided. The method for error handling of an interconnection protocol is for use in a first device that is linkable to a second device according to the interconnection protocol, the method comprising: during or after a power mode change of a link between the first device and the second device: a) triggering, by the first device, a first line reset signal to the second device; b) performing, by the first device, suppression of detected rate overlap errors; and c) stopping the suppression of detected rate overlap errors after the first device receives a second line reset signal from the second device.