公开(公告)号：US20240160574A1

公开(公告)日：2024-05-16

申请号：US18311896

申请日：2023-05-04

Applicant: SK hynix Inc.

Inventor： Yun Jeong MUN ,  Rak Kie KIM ,  Ho Kyoon LEE

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: A computer system may include a processor; a first memory device; a second memory device; a cache memory including a plurality of cache entries and a cache controller. The cache controller is configured to manage a source indicating whether a caching data is provided from the first memory device or the second memory device, and determine a cache entry to be evicted from the cache entries based on a cache miss ratio of request data by the source which the request data is read when the request data of the processor do not exist in the cache memory and a cache occupancy ratio by the source.

公开(公告)号：US20170123896A1

公开(公告)日：2017-05-04

申请号：US15061412

申请日：2016-03-04

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK ,  Jang Ryul KIM ,  Il PARK ,  Ho Kyoon LEE

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/10 ,  G06F11/1048 ,  G06F11/1076

Abstract: An on-chip logic block may include a host ECC circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ECC circuit configured to correct an error based on memory parity.

公开(公告)号：US20170271308A1

公开(公告)日：2017-09-21

申请号：US15174465

申请日：2016-06-06

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK ,  Il PARK ,  Ho Kyoon LEE ,  Young Pyo JOO

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H05K1/181 ,  H05K2201/09027 ,  H05K2201/10515

Abstract: A stack chip package may include a plurality of stacked semiconductor chips. Each of the semiconductor chips may have a first node, a second node, a third node and a fourth node corresponding to corners of the semiconductor chip. The plurality of semiconductor chips may be sequentially stacked such that, when a semiconductor chip is disposed directly on another semiconductor chip, the first node of the semiconductor chip is positioned over a side between the first node and the second node of the another semiconductor chip.

公开(公告)号：US20240126469A1

公开(公告)日：2024-04-18

申请号：US18173085

申请日：2023-02-23

Applicant: SK hynix Inc.

Inventor： Ho Kyoon LEE ,  Kwang Jin KO ,  Jun Hee RYU

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0625 ,  G06F3/0683

Abstract: A pooled memory device includes plural memory devices and a controller. The plural memory devices include a first memory and a second memory with at least one power supply configured to control power supplied to each of the plural memory devices. The controller is coupled to an interconnect device which is configured to provide the plural memory devices to at least one external device as a logical device. The controller is configured to track available storage capacities of the first memory and the second memory and cut off power supplied to an unused memory among the first memory and the second memory.