公开(公告)号：US20170123896A1

公开(公告)日：2017-05-04

申请号：US15061412

申请日：2016-03-04

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK ,  Jang Ryul KIM ,  Il PARK ,  Ho Kyoon LEE

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/10 ,  G06F11/1048 ,  G06F11/1076

Abstract: An on-chip logic block may include a host ECC circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ECC circuit configured to correct an error based on memory parity.

公开(公告)号：US20170271308A1

公开(公告)日：2017-09-21

申请号：US15174465

申请日：2016-06-06

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK ,  Il PARK ,  Ho Kyoon LEE ,  Young Pyo JOO

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H05K1/181 ,  H05K2201/09027 ,  H05K2201/10515

Abstract: A stack chip package may include a plurality of stacked semiconductor chips. Each of the semiconductor chips may have a first node, a second node, a third node and a fourth node corresponding to corners of the semiconductor chip. The plurality of semiconductor chips may be sequentially stacked such that, when a semiconductor chip is disposed directly on another semiconductor chip, the first node of the semiconductor chip is positioned over a side between the first node and the second node of the another semiconductor chip.

公开(公告)号：US20190295975A1

公开(公告)日：2019-09-26

申请号：US16168653

申请日：2018-10-23

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK

IPC: H01L23/00 ,  H01L23/367 ,  H01L21/82 ,  H05K1/18

Abstract: A multi-chip package may include a plurality of semiconductor chips and a printed circuit board (PCB). Each of the semiconductor chips may have an upper surface, a bottom surface, and a plurality of side surfaces. Circuit terminals may be arranged on the upper surface. A plurality of side bonding pads may be arranged on one or more selected side surface among the side surfaces. The semiconductor chips may be mounted on the PCB. The PCB may be configured to surround the selected side surface on which the side bonding pads may be arranged.

公开(公告)号：US20240160525A1

公开(公告)日：2024-05-16

申请号：US18194511

申请日：2023-03-31

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK ,  Young Pyo JOO

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076

Abstract: A computing system comprises a memory and a controller, and the controller is configured to store a first type of data and a second type of data in the memory, to divide the first type of data into a first part and a second part, to generate parity information on the first part and to store the parity information in the memory, and a refresh interval of a region of the memory where the first type of data is stored is larger than a refresh interval of a region of the memory where the second type of data is stored.

公开(公告)号：US20240094927A1

公开(公告)日：2024-03-21

申请号：US18304345

申请日：2023-04-21

Applicant: SK hynix Inc.

Inventor： Jin Ho BAEK ,  Young Pyo JOO

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory controller includes: a data separator configured to separate host write data into upper data and lower data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing the upper data into a first storage region that is selected based on the first address in a memory, and one or more second commands for writing the lower data into a second storage region that is selected based on the second address in the memory; and a control block configured to control the address generator and the command generator to make a difference in power consumption between the first storage region and the second storage region.