公开(公告)号：US20180358556A1

公开(公告)日：2018-12-13

申请号：US15878257

申请日：2018-01-23

Applicant: SK hynix Inc.

Inventor： Dae-Gun KANG ,  Su-Jin CHAE ,  Sung-Kyu MIN ,  Myoung-Sub KIM ,  Chi-Ho KIM ,  Su-Yeon LEE

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/16 ,  H01L45/1675

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

公开(公告)号：US20210050036A1

公开(公告)日：2021-02-18

申请号：US17088334

申请日：2020-11-03

Applicant: SK hynix Inc.

Inventor： Myoung-Sub KIM ,  Tae-Hoon KIM ,  Hye-Jung CHOI ,  Seok-Man HONG

IPC: G11C5/02 ,  H01L27/22 ,  G11C13/00

Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

公开(公告)号：US20180005673A1

公开(公告)日：2018-01-04

申请号：US15638201

申请日：2017-06-29

Applicant: SK hynix Inc.

Inventor： Myoung-Sub KIM

IPC: G11C7/12 ,  G11C11/16 ,  G11C13/04

CPC classification number: G11C7/12 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C2013/0052 ,  G11C2213/31 ,  G11C2213/32

Abstract: An electronic device includes a semiconductor memory that includes: a memory cell coupled between first and second lines and having a specific resistance state; a first read circuit suitable for supplying a predetermined pattern of a read voltage to the first line to generate a cell current corresponding to the specific resistance state of the memory cell during a read operation mode; and a second read circuit suitable for generating read data based on the cell current flowing through the second line during the read operation mode.

公开(公告)号：US20210098036A1

公开(公告)日：2021-04-01

申请号：US17119821

申请日：2020-12-11

Applicant: SK hynix Inc.

Inventor： Seok-Man HONG ,  Myoung-Sub KIM ,  Tae-Hoon KIM

IPC: G11C7/10 ,  G11C7/22

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

公开(公告)号：US20200066315A1

公开(公告)日：2020-02-27

申请号：US16378926

申请日：2019-04-09

Applicant: SK hynix Inc.

Inventor： Seok-Man HONG ,  Myoung-Sub KIM ,  Tae-Hoon KIM

IPC: G11C7/10 ,  G11C7/22

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.