公开(公告)号：US20240276891A1

公开(公告)日：2024-08-15

申请号：US18343443

申请日：2023-06-28

Applicant: SK hynix Inc.

Inventor： Woo Tae LEE ,  Su Jee KIM

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/066 ,  H10B63/84 ,  H10N70/063 ,  H10N70/8613 ,  H10N70/883

Abstract: A semiconductor device may include first conductive lines extending in a first direction; second conductive lines extending in a second direction that intersects the first direction; memory cells disposed between the first conductive lines and the second conductive lines in a third direction perpendicular to each of the first and the second directions, each of the memory cells comprising a variable resistance pattern; first gap-fill patterns disposed between the memory cells and having first thermal conductivity; and second gap-fill patterns disposed on the first gap-fill patterns in the third direction and having second thermal conductivity lower than the first thermal conductivity, wherein an interface between each of the second gap-fill patterns and each a corresponding one of the first gap-fill patterns is disposed between an upper surface and a lower surface of the variable resistance pattern.

公开(公告)号：US20210020244A1

公开(公告)日：2021-01-21

申请号：US17039480

申请日：2020-09-30

Applicant: SK hynix Inc.

Inventor： Sang Hyun BAN ,  Beom Seok LEE ,  Woo Tae LEE ,  Tae Hoon KIM ,  Hwan Jun ZANG ,  Hye Jung CHOI

IPC: G11C13/00

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.

公开(公告)号：US20240172571A1

公开(公告)日：2024-05-23

申请号：US18305914

申请日：2023-04-24

Applicant: SK hynix Inc.

Inventor： Woo Tae LEE

IPC: H10N70/00 ,  G11C13/00

CPC classification number: H10N70/826 ,  G11C13/0026 ,  G11C13/0028 ,  H10N70/063 ,  H10N70/066

Abstract: A semiconductor device and a method for fabricating the same may be provided. The semiconductor device may include: a first semiconductor structure including a substrate, a plurality of first word lines, a plurality of first bit lines, and a plurality of first memory cells respectively disposed in intersection regions between the first word lines and the first bit lines; and a second semiconductor structure including a plurality of second bit lines disposed over the first bit lines and respectively contacting the first bit lines, a plurality of second word lines, and a plurality of second memory cells respectively disposed in intersection regions between the second word lines and the second bit lines, wherein a first bit line and a corresponding second bit line form a metal-to-metal bonding.

公开(公告)号：US20210013409A1

公开(公告)日：2021-01-14

申请号：US16711286

申请日：2019-12-11

Applicant: SK hynix Inc.

Inventor： Woo Tae LEE ,  Beom Seok LEE

IPC: H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12

Abstract: A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.

公开(公告)号：US20240341104A1

公开(公告)日：2024-10-10

申请号：US18447196

申请日：2023-08-09

Applicant: SK hynix Inc.

Inventor： Woo Tae LEE

IPC: H10B63/00

CPC classification number: H10B63/80

Abstract: A semiconductor device may include a word line that extends in a first direction, a bit line that extends in a second direction that intersects the first direction, a variable resistance pattern that is disposed between the word line and the bit line and that has a first width in the first direction and a second width in the second direction, wherein the first width and the second width are different from each other, and an electrode pattern that is disposed between the variable resistance pattern and the bit line and that has a third width in the first direction and a fourth width in the second direction, wherein the third width and the fourth width are different from each other.

公开(公告)号：US20210083185A1

公开(公告)日：2021-03-18

申请号：US16855760

申请日：2020-04-22

Applicant: SK hynix Inc.

Inventor： Gwang Sun JUNG ,  Sang Hyun BAN ,  Jun Ku AHN ,  Beom Seok LEE ,  Young Ho LEE ,  Woo Tae LEE ,  Jong Ho LEE ,  Hwan Jun ZANG ,  Sung Lae CHO ,  Ye Cheon CHO ,  Uk HWANG

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 3 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 3 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 3 element.