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    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    1.
    发明申请
    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权
    访问设备，其制造方法和具有该接收设备的半导体存储器件

    公开(公告)号：US20140054532A1

    公开(公告)日：2014-02-27

    申请号：US13713534

    申请日：2012-12-13

    Applicant: SK HYNIX INC.

    Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

    IPC: H01L29/36 ,  H01L21/02

    CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

    Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

    3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    3D半导体集成电路装置及其制造方法

    公开(公告)号：US20160042960A1

    公开(公告)日：2016-02-11

    申请号：US14540866

    申请日：2014-11-13

    Applicant: SK hynix Inc.

    Inventor： Jin Ha KIM ,  Jun Kwan KIM ,  Kang Sik CHOI ,  Su Jin CHAE ,  Young Ho LEE

    IPC: H01L21/285 ,  H01L29/78 ,  H01L29/45 ,  H01L27/24

    CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/2454 ,  H01L29/456

    Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

    Abstract translation: 提供了一种3D半导体集成电路器件及其制造方法。 在半导体衬底上形成有源柱，并且形成层间绝缘层，使得有源柱埋在层间绝缘层中。 蚀刻层间绝缘层以形成孔，使得活性柱和活性柱的周边区域露出。 在通过孔暴露一定深度的有源柱的周边区域进行蚀刻处理，并且在有源柱和层间绝缘层之间设置具有深度的空间。 形成硅材料层以埋在具有深度的空间中，并且在硅材料层和有源支柱上形成欧姆接触层。

    FABRICATION METHOD OF SEMICONDUCTOR APPARATUS
    4.
    发明申请
    FABRICATION METHOD OF SEMICONDUCTOR APPARATUS 有权
    半导体器件制造方法

    公开(公告)号：US20140179069A1

    公开(公告)日：2014-06-26

    申请号：US13845770

    申请日：2013-03-18

    Applicant: SK HYNIX INC.

    Inventor： Young Ho LEE ,  Seung Beom BAEK

    IPC: H01L29/66

    CPC classification number: H01L21/84 ,  H01L21/7624 ,  H01L27/1203

    Abstract: A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer.

    Abstract translation: 一种制造半导体装置的方法包括在半导体衬底上形成绝缘层，在绝缘层中形成源极柱，并在源极和绝缘层上形成半导体层。

    PVD CHAMBER SHIELD STRUCTURE INCLUDING IMPROVED COTAING LAYER OR SHIELD
    5.
    发明申请
    PVD CHAMBER SHIELD STRUCTURE INCLUDING IMPROVED COTAING LAYER OR SHIELD 有权

    公开(公告)号：US20220310372A1

    公开(公告)日：2022-09-29

    申请号：US17474831

    申请日：2021-09-14

    Applicant: SK hynix Inc.

    Inventor： Gwang Sun JUNG ,  Jun Ku AHN ,  Young Ho LEE ,  Jong Ho LEE ,  Uk HWANG

    IPC: H01J37/34 ,  C23C14/34

    Abstract: A PVD chamber shield includes: a shield configured to surround a space between a sputtering target and a substrate that are disposed in a PVD chamber body, the shield having a hollow shape with an inner surface and an outer surface; and a coating layer formed over the inner surface of the shield. The coating layer has i) a dielectric constant not greater than a dielectric constant of a material deposited over the substrate, ii) a porosity greater than 0 vol % and less than 100 vol %, and iii) a thickness greater than 150 pm and less than a given upper limit, the upper limit being set to prevent an occurrence of peeling of a material deposited over the coating layer.

    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    8.
    发明申请
    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权
    访问设备，其制造方法和具有该接收设备的半导体存储器件

    公开(公告)号：US20150200088A1

    公开(公告)日：2015-07-16

    申请号：US14668330

    申请日：2015-03-25

    Applicant: SK hynix Inc.

    Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

    IPC: H01L21/02

    CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

    Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

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