公开(公告)号：US20250169154A1

公开(公告)日：2025-05-22

申请号：US18928190

申请日：2024-10-28

Applicant: SK hynix Inc.

Inventor： Kwan Woo DO ,  Hyung Keun KIM ,  Ye Cheon CHO ,  Jae Sang LEE

IPC: H01L29/49 ,  H01L29/423

Abstract: A semiconductor device includes a trench formed in a substrate, a gate insulation layer formed to contact a bottom surface and sidewall surfaces of the trench, a first electrode layer formed to contact the gate insulation layer, the first electrode layer comprising titanium, a second electrode layer formed to contact the first electrode layer, the second electrode layer comprising molybdenum and titanium, and a third electrode layer formed to contact the second electrode layer.

公开(公告)号：US20210083185A1

公开(公告)日：2021-03-18

申请号：US16855760

申请日：2020-04-22

Applicant: SK hynix Inc.

Inventor： Gwang Sun JUNG ,  Sang Hyun BAN ,  Jun Ku AHN ,  Beom Seok LEE ,  Young Ho LEE ,  Woo Tae LEE ,  Jong Ho LEE ,  Hwan Jun ZANG ,  Sung Lae CHO ,  Ye Cheon CHO ,  Uk HWANG

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 3 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 3 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 3 element.