公开(公告)号：US20230305922A1

公开(公告)日：2023-09-28

申请号：US17703362

申请日：2022-03-24

Applicant: SMART Modular Technologies, Inc.

Inventor： Robert Tower Frey ,  Kelvin Marino

IPC: G06F1/30 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F1/30 ,  G06F11/0772 ,  G06F11/0793 ,  G06F13/4282

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

公开(公告)号：US20240134757A1

公开(公告)日：2024-04-25

申请号：US18400185

申请日：2023-12-29

Applicant: SMART Modular Technologies, Inc.

Inventor： Torry Steed ,  Kelvin Marino ,  Jinying Shen ,  Itsik Yomorta

IPC: G06F11/14 ,  G06F1/26 ,  G06F1/30

CPC classification number: G06F11/1469 ,  G06F1/263 ,  G06F1/30 ,  G06F11/1451

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system includes: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device through the serial host interface based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device through the serial host interface. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

公开(公告)号：US12169436B2

公开(公告)日：2024-12-17

申请号：US17703362

申请日：2022-03-24

Applicant: SMART Modular Technologies, Inc.

Inventor： Robert Tower Frey ,  Kelvin Marino

IPC: G06F11/10 ,  G06F1/30 ,  G06F11/07 ,  G06F11/14 ,  G06F13/42

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

公开(公告)号：US09779016B1

公开(公告)日：2017-10-03

申请号：US13940118

申请日：2013-07-11

Applicant: SMART Modular Technologies, Inc.

Inventor： Jinying Shen ,  Robert Tower Frey ,  Kelvin Marino

IPC: G06F12/00 ,  G06F12/02 ,  G06F11/14 ,  G06F1/30 ,  G06F11/07

CPC classification number: G06F12/0246 ,  G06F1/28 ,  G06F1/30 ,  G06F11/0754 ,  G06F11/1456 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/314

Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.