公开(公告)号：US10826989B2

公开(公告)日：2020-11-03

申请号：US14512624

申请日：2014-10-13

Applicant: SMART Modular Technologies, Inc.

Inventor： Fong-Long Lin ,  Michael Rubino

IPC: H04L29/08

Abstract: A data storage system, and a method of operation thereof, includes: a host initialization module for initializing a data storage unit; a command process module, coupled to the host initialization module, for processing a read command or a write command performed on the data storage unit; and a status scheduler module, coupled to the command process module, for generating a check status request to inquire a storage unit status of the data storage unit, wherein the check status request occurs without interrupting a host.

公开(公告)号：US20160105510A1

公开(公告)日：2016-04-14

申请号：US14512624

申请日：2014-10-13

Applicant: SMART Modular Technologies, Inc.

Inventor： Fong-Long Lin ,  Michael Rubino

IPC: H04L29/08

Abstract: A data storage system, and a method of operation thereof, includes: a host initialization module for initializing a data storage unit; a command process module, coupled to the host initialization module, for processing a read command or a write command performed on the data storage unit; and a status scheduler module, coupled to the command process module, for generating a check status request to inquire a storage unit status of the data storage unit, wherein the check status request occurs without interrupting a host.

Abstract translation: 数据存储系统及其操作方法包括：主机初始化模块，用于初始化数据存储单元; 命令处理模块，耦合到所述主机初始化模块，用于处理对所述数据存储单元执行的读取命令或写入命令; 以及状态调度器模块，其耦合到所述命令处理模块，用于生成查询数据存储单元的存储单元状态的检查状态请求，其中所述检查状态请求发生而不中断主机。

公开(公告)号：US20170262337A1

公开(公告)日：2017-09-14

申请号：US15066728

申请日：2016-03-10

Applicant: SMART Modular Technologies, Inc.

Inventor： Reuben J. Chang ,  Satyanarayan S. Iyer ,  Michael Rubino

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04 ,  G06F13/24

CPC classification number: G11C29/04 ,  G06F13/24 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/50 ,  G11C29/52 ,  G11C2029/4402

Abstract: A memory module repair system, and a method of operation thereof, including: a memory controller; a volatile memory having memory chips coupled to the memory controller, the memory controller for testing the volatile memory; an ECC controller, coupled to the memory controller, for determining a failing bit location information of a failing bit within the volatile memory; and an error log storage coupled to the memory controller and the ECC controller for storing the failing bit location information.