公开(公告)号：US20220109073A1

公开(公告)日：2022-04-07

申请号：US17643839

申请日：2021-12-13

Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY

Inventor： Rongsheng CHEN ,  Lelong YAN ,  Wei ZHONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/45 ,  H01L29/66

Abstract: The present disclosure discloses a passivation layer and a preparation method thereof, a flexible thin film transistor and a preparation method thereof, and an array substrate. The passivation layer of the present disclosure is a self-assembled monolayer formed by hydrophobic substances with a melting point of less than 100° C. The flexible thin film transistor of the present disclosure comprises a flexible substrate, a gate electrode, a gate dielectric layer, an active layer, a source-drain electrode layer and the passivation layer of the present disclosure.

公开(公告)号：US20220116001A1

公开(公告)日：2022-04-14

申请号：US17385020

申请日：2021-07-26

Applicant: South China University of Technology

Inventor： Rongsheng CHEN ,  Mingzhu WEN ,  Yuming XU ,  Hui LI

IPC: H03F3/45 ,  H03F1/02 ,  H03F1/08

Abstract: Disclosed is an operational amplifier based on a metal-oxide TFT. The operational amplifier includes an auxiliary amplifier and a bootstrap gain-increasing amplifier. The auxiliary amplifier adopts a two-stage positive feedback structure, including a fifth transistor, a seventh transistor, an eleventh transistor, a first amplifying unit, and a second amplifying unit. A gate of the fifth transistor serves as an input end of the operational amplifier. The bootstrap gain-increasing amplifier includes two second circuits in mutual symmetry. Each of the second circuits includes a first transistor, a second transistor, and a current source unit with a bootstrap structure.

公开(公告)号：US20200350167A1

公开(公告)日：2020-11-05

申请号：US16758678

申请日：2017-11-08

Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY

Inventor： Rongsheng CHEN ,  Sunbin DENG ,  Hoising KWOK

IPC: H01L21/02 ,  H01L29/24 ,  H01L29/786 ,  C23C14/08 ,  C23C14/58

Abstract: Disclosed is an inorganic metal oxide thin film with an embedded crystal morphology, wherein the embedded crystal morphology is composed of crystalline grains and an amorphous matrix, the crystalline grains are embedded in the amorphous matrix, and the grain size ranges from 0.5 nm to 10 nm. Also provided is a manufacturing method of the inorganic metal oxide thin film with the embedded crystal morphology.

公开(公告)号：US20220182021A1

公开(公告)日：2022-06-09

申请号：US17593844

申请日：2019-12-31

Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY

Inventor： Rongsheng CHEN ,  Houbo FAN ,  Guoyuan LI ,  Yuming XU ,  Yuning QIN ,  Zhaohui WU ,  Bin LI

IPC: H03F1/34 ,  H03G3/30

Abstract: The present disclosure discloses a thin film transistor (TFT)-based bootstrap structure amplifier, and a chip. The amplifier includes an input circuit, an output buffer, and several bootstrap structure units. The bootstrap structure units include a TFT and a capacitor. The drain and the gate of the TFT are both connected to the same voltage node. The source of the TFT is connected to one end of the capacitor. The other end of the capacitor is connected to an output signal node. The output buffer is formed by connecting the sources and drains of several TFTs in series. Two ends of the output buffer are respectively connected to an input voltage node and an output signal node. The source of the TFT in each bootstrap structure unit is connected to the gates of the TFTs in one output buffer. The input circuit includes an input signal node, the output signal node, and a grounding node. The present disclosure can increase circuit gain and have a simple structure and low fabrication cost. The present disclosure can be widely applied to the field of integrated circuits.

公开(公告)号：US20220116046A1

公开(公告)日：2022-04-14

申请号：US17386678

申请日：2021-07-28

Applicant: South China University of Technology

Inventor： Rongsheng CHEN ,  Hui LI ,  Yuming XU ,  Mingzhu WEN

IPC: H03L7/08 ,  H03K17/687

Abstract: Disclosed is a charge-pump phase-locked loop based on a unipolar thin film transistor, a chip, and a method. The phase-locked loop may include: a phase-frequency detector, configured to detect a phase difference and a frequency difference between a clock Fref and a clock Fn and generate control signals UP and DOWN; a logic control module, configured to output logic state signals; a charge pump, configured to convert the logic state signals into a charging/discharging current signal; a low-pass filter, configured to output a direct-current analog control signal Vctrl; a voltage-controlled oscillator, configured to adjust an output clock frequency Fvco; and a divide-by-four circuit, configured to perform frequency division to obtain the clock Fn.