公开(公告)号：US20160246807A1

公开(公告)日：2016-08-25

申请号：US15145383

申请日：2016-05-03

Applicant: Super Talent Technology Corp.

Inventor： Frank Yu ,  Abraham C. Ma ,  Shimon Chen ,  Yao-Tse Chang ,  Yan Zhou

IPC: G06F17/30 ,  G06F12/10 ,  G06F11/10 ,  G06F3/06 ,  G06F12/14 ,  G06F12/08 ,  G06F12/02

CPC classification number: G06F11/1072 ,  G06F11/1016 ,  G06F11/1044 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1408 ,  G06F17/30132 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G11C14/0018 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/353 ,  H03M13/356

Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.

Abstract translation: 连接到主机DRAM的GNSD驱动器，并具有存储器管理器，数据分组器引擎，数据非分组引擎，电源管理器和刷新/恢复管理器。 GNSD驱动程序与GNSD应用程序相连，主机DRAM耦合到非易失性存储器设备。 GNSD驱动程序还包括压缩/解压缩引擎，重复数据删除引擎，加密/解密引擎或高级错误纠正码引擎。 加密/解密引擎根据DES或AES进行加密。 操作与主机的DRAM耦合的GNSD驱动程序和GNSD应用程序的方法包括：将主机和GNSD应用程序的配置和注册O / S设置进行耦合; 数据分组器和数据未分组到主机DRAM和上和下滤波器; 电源管理器和内存管理器; DRAM的刷新/恢复管理器; 和DRAM到SEED SSD。

公开(公告)号：US09489258B2

公开(公告)日：2016-11-08

申请号：US15145383

申请日：2016-05-03

Applicant: Super Talent Technology Corp.

Inventor： Frank Yu ,  Abraham C. Ma ,  Shimon Chen ,  Yao-Tse Chang ,  Yan Zhou

IPC: G11C29/00 ,  G06F11/10 ,  G06F17/30 ,  G06F12/08 ,  G06F12/10 ,  G06F12/02 ,  G06F12/14

CPC classification number: G06F11/1072 ,  G06F11/1016 ,  G06F11/1044 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1408 ,  G06F17/30132 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G11C14/0018 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/353 ,  H03M13/356

Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.

Abstract translation: 连接到主机DRAM的GNSD驱动器，并具有存储器管理器，数据分组器引擎，数据非分组引擎，电源管理器和刷新/恢复管理器。 GNSD驱动程序与GNSD应用程序相连，主机DRAM耦合到非易失性存储器设备。 GNSD驱动程序还包括压缩/解压缩引擎，重复数据删除引擎，加密/解密引擎或高级错误纠正码引擎。 加密/解密引擎根据DES或AES进行加密。 操作与主机的DRAM耦合的GNSD驱动程序和GNSD应用程序的方法包括：将主机和GNSD应用程序的配置和注册O / S设置进行耦合; 数据分组器和数据未分组到主机DRAM和上和下滤波器; 电源管理器和内存管理器; DRAM的刷新/恢复管理器; 和DRAM到SEED SSD。

公开(公告)号：US20190294345A1

公开(公告)日：2019-09-26

申请号：US15928014

申请日：2018-03-21

Applicant: Super Talent Technology Corp.

Inventor： Frank Yu ,  Abraham C. Ma ,  Shimon Chen ,  Yao-Tse Chang ,  Yan Zhou

IPC: G06F3/06 ,  G06F12/1009

Abstract: A Green NAND SSD (GNSD) controller receives reads and writes from a host and writes to flash memory. A SSD DRAM has a DRAM Translation Layer (ETL) with buffers managed by the GNSD controller. The GNSD controller performs deduplication, compression, encryption, high-level error-correction, and grouping of host data writes, and manages mapping tables to store host write data in the SSD DRAM to reduce writes to flash memory. The GNSD controller categorizes host writes as data types for paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the GNSD controller. Status bits include two overwrite bits indicating frequently-written data that is retained in the SSD DRAM rather than being flushed to flash and re-allocated.

公开(公告)号：US09123422B2

公开(公告)日：2015-09-01

申请号：US13788989

申请日：2013-03-07

Applicant: Super Talent Technology, Corp.

Inventor： Frank Yu ,  Abraham C. Ma ,  Shimon Chen ,  Yao-Tse Chang

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C16/10 ,  G06F12/02 ,  G11C13/00 ,  G11C29/00

CPC classification number: G11C16/10 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C13/0004 ,  G11C29/765 ,  G11C2211/5641

Abstract: An retention flash controller reads assigned-level bits from a bad block/erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

Abstract translation: 保留闪存控制器从坏块/擦除计数表或从指示闪存单元作为三级单元（TLC），多级单元（MLC）或者多级别单元（MLC））操作的页状态表读取分配级位 单级单元（SLC）。 通过更改分配的级别位，降级为TLC或MLC的页面被降级以用作SLC页面。 电平位调整由接收来自读取位线的电压比较器的输入的转换逻辑使用的真值表。 每个逻辑电平的电压范围可以通过真值表或可编程寄存器进行调整。 可以调节编程电压或编程脉冲，以增加持续性和允许的编程擦除周期的数量，同时在闪存单元需要刷新之前减少保留时间。 闪存的混合配置具有MLC块和MLC作为SLC块或其他组合。

公开(公告)号：US20140006688A1

公开(公告)日：2014-01-02

申请号：US13788989

申请日：2013-03-07

Applicant: SUPER TALENT TECHNOLOGY, CORP.

Inventor： Frank Yu ,  Abraham C. Ma ,  Shimon Chen ,  Yao-Tse Chang

IPC: G11C16/10 ,  G06F12/02

CPC classification number: G11C16/10 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C13/0004 ,  G11C29/765 ,  G11C2211/5641

Abstract: An retention flash controller reads assigned-level bits from a bad block/erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

Abstract translation: 保留闪存控制器从坏块/擦除计数表或从指示闪存单元作为三级单元（TLC），多级单元（MLC）或者多级别单元（MLC））操作的页状态表读取分配级位 单级单元（SLC）。 通过更改分配的级别位，降级为TLC或MLC的页面被降级以用作SLC页面。 电平位调整由接收来自读取位线的电压比较器的输入的转换逻辑使用的真值表。 每个逻辑电平的电压范围可以通过真值表或可编程寄存器进行调整。 可以调节编程电压或编程脉冲，以增加持续性和允许的编程擦除周期的数量，同时在闪存单元需要刷新之前减少保留时间。 闪存的混合配置具有MLC块和MLC作为SLC块或其他组合。