公开(公告)号：US20160021744A1

公开(公告)日：2016-01-21

申请号：US14735870

申请日：2015-06-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Young Gwan KO ,  Jung Hyun CHO ,  Jae Ean LEE ,  Jae Hoon CHOI ,  Jung Hyun PARK

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/113 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H01L2924/00

Abstract: A printed circuit board includes a first circuit pattern embedded in an insulating layer so that an upper surface of the first circuit pattern is exposed to one surface of the insulating layer, a coupling pad embedded in the insulating layer to come into contact with a lower surface of the first circuit pattern, and a bump pad formed on the upper surface of the first circuit pattern to protrude from one surface of the insulating layer.

Abstract translation: 印刷电路板包括嵌入在绝缘层中的第一电路图案，使得第一电路图案的上表面暴露于绝缘层的一个表面，嵌入在绝缘层中以与下表面接触的耦合垫 以及形成在第一电路图案的上表面上以从绝缘层的一个表面突出的凸块焊盘。

公开(公告)号：US20190164876A1

公开(公告)日：2019-05-30

申请号：US15919507

申请日：2018-03-13

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Ean LEE ,  Tae Sung JEONG ,  Young Gwan KO ,  Ik Jun CHOI ,  Jung Soo BYUN

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/78 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/78 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/53228 ,  H01L2221/68318

Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

公开(公告)号：US20190131221A1

公开(公告)日：2019-05-02

申请号：US15913429

申请日：2018-03-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Ean LEE ,  Tae Sung JEONG ,  Young Gwan KO ,  Suk Ho LEE ,  Jung Soo BYUN

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

公开(公告)号：US20150342054A1

公开(公告)日：2015-11-26

申请号：US14667001

申请日：2015-03-24

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Hyo Seung NAM ,  Jae Ean LEE ,  Ju Yeon BONG ,  Jung Hyun CHO ,  Kyung Hwan KO

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/32 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/10 ,  H05K1/182 ,  H05K3/284 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2201/10015 ,  Y10T29/49156

Abstract: Embodiments of the invention provide an embedded coreless substrate, and a method for manufacturing the same. According to an embodiment of the present invention, an embedded coreless substrate includes an insulating layer, a conductive pattern including a plurality of circuit pattern layers formed in(on) the insulating layer and a plurality of vias for vertically connecting the circuit pattern layers, and at least one embedded device, which is partially embedded in the insulating layer and an outer circuit pattern layer among the plurality of circuit pattern layers and of which an electrode in an embedded portion is partially or entirely covered with the outer circuit pattern layer to fix the embedded portion, is provided. Further, a method for manufacturing an embedded coreless substrate is provided.

Abstract translation: 本发明的实施例提供一种嵌入式无芯基板及其制造方法。 根据本发明的实施例，嵌入式无芯基板包括绝缘层，包括形成在绝缘层中的多个电路图案层的导电图案和用于垂直连接电路图案层的多个通孔，以及 部分嵌入绝缘层中的至少一个嵌入式装置和多个电路图案层之中的外部电路图案层，并且其中嵌入部分中的电极部分或全部被外部电路图案层覆盖以将 嵌入式部分。 此外，提供了一种用于制造嵌入式无芯基板的方法。

公开(公告)号：US20150251278A1

公开(公告)日：2015-09-10

申请号：US14448150

申请日：2014-07-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Ean LEE ,  Jung Hyun CHO ,  Kyung Hwan KO ,  Yong Ho BAEK

IPC: B23K35/02 ,  H05K1/18 ,  B23K35/24

CPC classification number: B23K35/0244 ,  B23K35/0222 ,  B23K35/0238 ,  B23K35/24 ,  B23K35/26 ,  B23K35/262 ,  B32B15/01 ,  C22C12/00 ,  C22C28/00 ,  C22C43/00 ,  H05K3/3463 ,  H05K3/3478 ,  H05K2203/041 ,  Y10T428/12493 ,  Y10T428/12681

Abstract: A solder ball has a core, an intermediate layer, and a surface layer. In one aspect, the intermediate layer melts at a temperature higher than that of the surface layer. In another aspect, the core is made of a material that maintains a liquid state through a temperature range of from about 20° C. to about 110° C., the intermediate layer is made of a material that maintains a solid state at temperatures up to about 270° C., and the surface layer is made of a material with a melting temperature of about 230° C. to about 270° C. In another aspect, the first metal and the second metal are materials that do not form an intermetallic compound with another material in the solder ball. The solder ball may be used in a circuit board.

Abstract translation: 焊球具有芯，中间层和表面层。 在一个方面，中间层在高于表面层的温度下熔化。 在另一方面，芯由保持液态在约20℃至约110℃的温度范围内的材料制成，中间层由在高温下保持固态的材料制成 至约270℃，表面层由熔点为约230℃至约270℃的材料制成。在另一方面，第一金属和第二金属是不形成 金属间化合物与焊球中的另一种材料。 焊球可用于电路板。

公开(公告)号：US20190259697A1

公开(公告)日：2019-08-22

申请号：US16399540

申请日：2019-04-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Ean LEE ,  Tae Sung JEONG ,  Young Gwan KO ,  Ik Jun CHOI ,  Jung Soo BYUN

IPC: H01L23/498 ,  H01L21/78 ,  H01L23/532 ,  H01L23/15 ,  H01L21/56

Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

公开(公告)号：US20190229070A1

公开(公告)日：2019-07-25

申请号：US16105956

申请日：2018-08-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yi Eok KWON ,  Jae Ean LEE ,  Hak Young LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065

Abstract: A fan-out semiconductor package includes: a semiconductor chip; a redistribution portion disposed below the semiconductor chip; a reinforcing member disposed on the redistribution portion and surrounding the semiconductor chip; and an encapsulant disposed on the redistribution portion to embed the semiconductor chip and the reinforcing member therein.

公开(公告)号：US20190229060A1

公开(公告)日：2019-07-25

申请号：US16375302

申请日：2019-04-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Sang Kun KIM ,  Ye Jeong KIM ,  Jae Ean LEE ,  Jae Hoon CHOI

IPC: H01L23/538 ,  H01L21/66 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.

公开(公告)号：US20180269156A1

公开(公告)日：2018-09-20

申请号：US15982839

申请日：2018-05-17

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Sang Kun KIM ,  Ye Jeong KIM ,  Jae Ean LEE ,  Jae Hoon CHOI

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H05K1/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L22/14 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/215 ,  H01L2224/24265 ,  H01L2224/82005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19102 ,  H05K1/186

Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.

公开(公告)号：US20170213794A1

公开(公告)日：2017-07-27

申请号：US15385414

申请日：2016-12-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Sang Kun KIM ,  Ye Jeong KIM ,  Jae Ean LEE ,  Jae Hoon CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/66 ,  H01L21/48 ,  H01L21/56 ,  H05K1/18 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L22/14 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/215 ,  H01L2224/24265 ,  H01L2224/82005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19102 ,  H05K1/186

Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.