公开(公告)号：US12139814B2

公开(公告)日：2024-11-12

申请号：US18298692

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok Lee ,  Hyeonsuk Shin ,  Hyeonjin Shin ,  Seokmo Hong ,  Minhyun Lee ,  Seunggeol Nam ,  Kyungyeol Ma

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US11996150B2

公开(公告)日：2024-05-28

申请号：US17540675

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol Nam ,  Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

公开(公告)号：US11984514B2

公开(公告)日：2024-05-14

申请号：US18324638

申请日：2023-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC classification number: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US11676999B2

公开(公告)日：2023-06-13

申请号：US17072737

申请日：2020-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Jo ,  Eunha Lee ,  Jinseong Heo ,  Junghwa Kim ,  Hyangsook Lee ,  Seunggeol Nam

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L23/29

CPC classification number: H01L29/0649 ,  H01L23/291 ,  H01L29/4236 ,  H01L29/66977

Abstract: An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.

公开(公告)号：US11342414B2

公开(公告)日：2022-05-24

申请号：US17001925

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Haeryong Kim ,  Hyeonjin Shin ,  Seunggeol Nam ,  Seongjun Park

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285 ,  H01L29/45 ,  H01L29/16 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

公开(公告)号：US10727182B2

公开(公告)日：2020-07-28

申请号：US16257189

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Yeonchoo Cho ,  Seongjun Park ,  Hyeonjin Shin ,  Jaeho Lee

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20200039827A1

公开(公告)日：2020-02-06

申请号：US16233513

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alum JUNG ,  Keunwook Shin ,  Kyung-Eun Byun ,  Hyeonjin Shin ,  Hyunseok Lim ,  Seunggeol Nam ,  Hyunjae Song ,  Yeonchoo Cho

IPC: C01B32/186 ,  C23C16/26 ,  C23C16/505 ,  C23C16/511 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04

Abstract: A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

公开(公告)号：US10134628B2

公开(公告)日：2018-11-20

申请号：US15172908

申请日：2016-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Seongjun Park ,  Keunwook Shin ,  Hyeonjin Shin ,  Jaeho Lee ,  Changseok Lee ,  Yeonchoo Cho

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/285 ,  H01L29/45

Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.

公开(公告)号：US12217958B2

公开(公告)日：2025-02-04

申请号：US16807702

申请日：2020-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Janghee Lee ,  Seunggeol Nam ,  Hyeonjin Shin ,  Hyunseok Lim ,  Alum Jung ,  Kyung-Eun Byun ,  Jeonil Lee ,  Yeonchoo Cho

IPC: C23C16/02 ,  C23C16/26 ,  H01L21/02

Abstract: A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

公开(公告)号：US12199165B2

公开(公告)日：2025-01-14

申请号：US17670949

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Kim ,  Seunggeol Nam ,  Keunwook Shin ,  Dohyun Lee

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.