公开(公告)号：US20240178236A1

公开(公告)日：2024-05-30

申请号：US18378832

申请日：2023-10-11

Applicant: Sharp Display Technology Corporation

Inventor： Yuhichi SAITOH ,  Atsushi HACHIYA ,  Hiroaki FURUKAWA

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343

CPC classification number: H01L27/124 ,  G02F1/136231 ,  G02F1/13685 ,  H01L27/1288 ,  G02F1/134318 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1225

Abstract: A display device includes a first semiconductor portion, a first insulating film, a first electrode, a second electrode, a second insulating film, a second semiconductor portion, a third insulating film, a third electrode, and a fourth electrode, the second insulating film is disposed to overlap at least the second semiconductor portion and is not formed in a range overlapping the first semiconductor portion, the first insulating film and the third insulating film are each provided with a first contact hole connecting the third electrode to the first semiconductor portion, and the third insulating film is provided with a second contact hole connecting the fourth electrode to the second semiconductor portion.

公开(公告)号：US20240085752A1

公开(公告)日：2024-03-14

申请号：US18237501

申请日：2023-08-24

Applicant: Sharp Display Technology Corporation

Inventor： Atsushi HACHIYA ,  Hiroaki FURUKAWA ,  Yuhichi SAITOH

IPC: G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/13685 ,  G02F1/136286

Abstract: An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.

公开(公告)号：US20230161210A1

公开(公告)日：2023-05-25

申请号：US17978312

申请日：2022-11-01

Applicant: Sharp Display Technology Corporation

Inventor： Atsushi HACHIYA ,  Hiroaki FURUKAWA ,  Yuhichi SAITOH ,  Kuniaki OKADA

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/136286 ,  H01L27/124 ,  G02F1/133345

Abstract: An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate. The first connection electrode is formed from a transparent conductive material.

公开(公告)号：US20240377690A1

公开(公告)日：2024-11-14

申请号：US18779420

申请日：2024-07-22

Applicant: Sharp Display Technology Corporation

Inventor： Atsushi HACHIYA ,  Hiroaki FURUKAWA ,  Yuhichi SAITOH

IPC: G02F1/1368 ,  G02F1/1362

Abstract: An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.

公开(公告)号：US20230168550A1

公开(公告)日：2023-06-01

申请号：US18070579

申请日：2022-11-29

Applicant: Sharp Display Technology Corporation

Inventor： Yuhichi SAITOH ,  Hiroaki FURUKAWA ,  Atsushi HACHIYA ,  Hiroshi MATSUKIZONO

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1339 ,  H01L27/12 ,  H01L29/786 ,  G09G3/36

CPC classification number: G02F1/136227 ,  G02F1/133388 ,  G02F1/1368 ,  G02F1/136209 ,  G02F1/134309 ,  G02F1/13394 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78633 ,  H01L29/7869 ,  H01L27/1288 ,  G09G3/3677 ,  G02F1/13439 ,  G02F2202/16 ,  G09G2310/0297

Abstract: An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.

公开(公告)号：US20250053050A1

公开(公告)日：2025-02-13

申请号：US18932853

申请日：2024-10-31

Applicant: Sharp Display Technology Corporation

Inventor： Yuhichi SAITOH ,  Hiroaki FURUKAWA ,  Atsushi HACHIYA ,  Hiroshi MATSUKIZONO

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.