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1.
公开(公告)号:US20240311044A1
公开(公告)日:2024-09-19
申请号:US18120973
申请日:2023-03-13
Applicant: Silicon Motion, Inc.
Inventor: Chia-Chi Liang , Cheng-Yu Tsai
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0622 , G06F3/0679
Abstract: A method for reading data from a flash memory is provided. The method comprises: determining whether a host device is requesting a sequential read access to the flash memory; prior to receiving a first host read command issued by the host device, performing a read-ahead operation to read data from the flash memory according to a read-ahead start logical block address (LBA) if the host device is requesting the sequential read access to the flash memory; and storing the data that is read through the read-ahead operation in a read-ahead buffer; and in response to receiving a first host read command issued by the host device, sending a portion or all of data that is read through the read-ahead operation to the host device if a start LBA of the first host read command corresponds to one of start LBAs of data that is stored in the read-ahead buffer.
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公开(公告)号:US20190107964A1
公开(公告)日:2019-04-11
申请号:US15859712
申请日:2018-01-01
Applicant: Silicon Motion Inc.
Inventor: Chia-Chi Liang , Jie-Hao Lee
Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing a checking operation to obtain a checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device; reading the target data and associated metadata from the NV memory, wherein a latest version of the L2P table is available in the RAM when reading the target data from the NV memory is performed; and checking whether a recorded logical address within the metadata and the logical address received from the host device are equivalent to each other, to control whether to send the target data to the host device.
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公开(公告)号:US09645895B2
公开(公告)日:2017-05-09
申请号:US14534569
申请日:2014-11-06
Applicant: Silicon Motion, Inc.
Inventor: Chien-Cheng Lin , Chia-Chi Liang , Chang-Chieh Huang , Jie-Hao Lee
CPC classification number: G06F11/1469 , G06F3/0604 , G06F3/0631 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F11/1072 , G06F11/141 , G06F11/1435 , G06F12/0246 , G06F12/0802 , G06F12/121 , G06F2212/1032 , G06F2212/60 , G06F2212/69 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/56 , G11C29/52 , G11C2029/0411 , G11C2211/5641 , Y02D10/13
Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to establish a first physical-to-logical address mapping table (F2H table) in a random access memory (RAM) for a first run-time write block containing MLCs. The microcontroller is further configured to establish a second F2H table in the RAM for a second run-time write block containing SLCs. When data that was previously stored in the first run-time write block with un-uploaded mapping information in the first F2H table is updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table (H2F table) in accordance with the first F2H table. The H2F table is provided within the flash memory.
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公开(公告)号:US12079483B2
公开(公告)日:2024-09-03
申请号:US17976901
申请日:2022-10-31
Applicant: Silicon Motion, Inc.
Inventor: Chia-Chi Liang , Hsiao-Chang Yen , Tsu-Han Lu
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0629 , G06F3/0679
Abstract: A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.
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公开(公告)号:US12061792B1
公开(公告)日:2024-08-13
申请号:US18122134
申请日:2023-03-16
Applicant: Silicon Motion, Inc.
Inventor: Meng-Hua Yang , Chia-Chi Liang
IPC: G06F3/06 , G06F12/1009
CPC classification number: G06F3/0607 , G06F3/0659 , G06F3/0679 , G06F12/1009
Abstract: A method for use in a flash memory to handle host write commands includes: performing a dummy pattern detection while programing data into a specific section of a first block or a first super block of the flash memory; setting a dummy pattern indicator if all the data that is programmed to the specific section of the first block or the first super block of the flash memory corresponds to a predetermined dummy pattern; and in response to host write commands, modifying a host-to-flash (H2F) address mapping table regarding data that is requested by the host write commands to be programmed to a second block or a second super block of the flash memory without programming the data into the second super block or the second block to complete the host write commands if the dummy pattern indicator is set.
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公开(公告)号:US09842030B2
公开(公告)日:2017-12-12
申请号:US15597742
申请日:2017-05-17
Applicant: Silicon Motion, Inc.
Inventor: Chien-Cheng Lin , Chia-Chi Liang , Chang-Chieh Huang , Jie-Hao Lee
CPC classification number: G06F11/1469 , G06F3/0604 , G06F3/0631 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F11/1072 , G06F11/141 , G06F11/1435 , G06F12/0246 , G06F12/0802 , G06F12/121 , G06F2212/1032 , G06F2212/60 , G06F2212/69 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/56 , G11C29/52 , G11C2029/0411 , G11C2211/5641 , Y02D10/13
Abstract: The data storage device included a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages, and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory. The microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory and records a link table indicator on the flash memory to indicate a position of the link table. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. Further, the microcontroller erases user of logical addresses corresponding to N logical-to-physical address mapping tables.
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公开(公告)号:US09542278B2
公开(公告)日:2017-01-10
申请号:US14534686
申请日:2014-11-06
Applicant: Silicon Motion, Inc.
Inventor: Chien-Cheng Lin , Chia-Chi Liang , Chang-Chieh Huang , Jie-Hao Lee
CPC classification number: G06F11/1469 , G06F3/0604 , G06F3/0631 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F11/1072 , G06F11/141 , G06F11/1435 , G06F12/0246 , G06F12/0802 , G06F12/121 , G06F2212/1032 , G06F2212/60 , G06F2212/69 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/56 , G11C29/52 , G11C2029/0411 , G11C2211/5641 , Y02D10/13
Abstract: A data storage device and a flash memory control method with high efficiency are disclosed. The random access memory of the data storage device is allocated to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table. When recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller of the data storage device is configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.
Abstract translation: 公开了一种高效率的数据存储装置和闪存控制方法。 分配数据存储装置的随机存取存储器以提供对应于记录到物理到逻辑地址映射表中的逻辑地址的逻辑到物理地址映射表的收集和更新区域。 当将没有出现在收集和更新区域中的新的逻辑到物理地址映射表对应的逻辑地址记录到物理到逻辑地址映射表中时,数据存储设备的微控制器被配置为收集 新的逻辑到物理地址映射表转换为收集和更新区域,并在收集和更新区域内执行新的逻辑到物理地址映射表的更新。
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公开(公告)号:US12141060B1
公开(公告)日:2024-11-12
申请号:US18144864
申请日:2023-05-09
Applicant: Silicon Motion, Inc.
Inventor: Chia-Chi Liang , Cheng-Yu Tsai
IPC: G06F12/02
Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.
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9.
公开(公告)号:US20190213137A1
公开(公告)日:2019-07-11
申请号:US16022714
申请日:2018-06-29
Applicant: Silicon Motion Inc.
Inventor: Chien-Cheng Lin , Chia-Chi Liang , Jie-Hao Lee
IPC: G06F12/10
CPC classification number: G06F12/10 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205
Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises: reading a logical address to physical address (L2P) mapping table from the flash memory module; compressing the L2P mapping table to generate a compressed mapping table, wherein the compressed mapping table records a reference physical address and whether a corresponding physical address of each logical address is the reference physical address plus an offset value; and when receiving a read command asking for reading data corresponding to a specific logical address, referring to the compressed mapping table to determine a specific physical address corresponding to the specific logical address, and reading the data from the flash memory module according to the specific physical address.
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公开(公告)号:US09727271B2
公开(公告)日:2017-08-08
申请号:US15437543
申请日:2017-02-21
Applicant: Silicon Motion, Inc.
Inventor: Chien-Cheng Lin , Chia-Chi Liang , Chang-Chieh Huang , Jie-Hao Lee
IPC: G06F3/06 , G11C11/56 , G06F12/08 , G06F12/0802
CPC classification number: G06F11/1469 , G06F3/0604 , G06F3/0631 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F11/1072 , G06F11/141 , G06F11/1435 , G06F12/0246 , G06F12/0802 , G06F12/121 , G06F2212/1032 , G06F2212/60 , G06F2212/69 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/56 , G11C29/52 , G11C2029/0411 , G11C2211/5641 , Y02D10/13
Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.
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