公开(公告)号：US07861029B2

公开(公告)日：2010-12-28

申请号：US12108366

申请日：2008-04-23

Applicant: Srdjan Djordjevic

Inventor： Srdjan Djordjevic

IPC: G06F12/00

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/12

Abstract: A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of each memory rank, and a selection signal output for the selection signal of each memory rank, the memory elements being arranged in rows on the board and the memory elements of a memory rank extending only over half of the rows.

Abstract translation: 一种存储器模块，具有在板上的板和多个属于不同存储器等级的存储器元件，每个存储器等级可通过相应的选择信号寻址。 存储器模块还包括具有耦合到每个存储器等级的存储器元件的存储器级接口的存储器缓冲器，以及用于每个存储器级别的选择信号的选择信号，存储器元件被布置在板上的行中，并且存储器 存储器级别的元素仅延伸超过一半行。

公开(公告)号：US20090037683A1

公开(公告)日：2009-02-05

申请号：US11833841

申请日：2007-08-03

Applicant: Srdjan Djordjevic

Inventor： Srdjan Djordjevic

IPC: G06F12/00

CPC classification number: G11C5/04

Abstract: A semiconductor memory arrangement includes a substrate, a first control device disposed on the substrate and adapted to receive command and address signals, a second control device, and a plurality of memory units. The second control device is adapted to receive the command and address signals from the first control device and to transmit the command and address signals to the memory units of the plurality of memory units.

Abstract translation: 半导体存储器装置包括衬底，设置在衬底上并适于接收命令和地址信号的第一控制装置，第二控制装置和多个存储器单元。 第二控制装置适于从第一控制装置接收命令和地址信号，并将命令和地址信号发送到多个存储器单元的存储器单元。

公开(公告)号：US07298668B2

公开(公告)日：2007-11-20

申请号：US11346570

申请日：2006-02-03

Applicant: Wolfgang Hoppe ,  Srdjan Djordjevic

Inventor： Wolfgang Hoppe ,  Srdjan Djordjevic

IPC: G11C8/00

CPC classification number: G11C5/04

Abstract: A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2R×4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside of the module board. In contrast to a “Stacked DRAM” design, the semiconductor components in accordance with the planar design contain only one memory chip. By using a parallel routing for a command address bus and an on-die termination bus, the address, clock, and control buses can be adapted in terms of load, so that different signal propagation times on the different buses are avoided to the greatest possible extent.

Abstract translation: 例如，形成为FBDIMM存储器模块的半导体存储器模块具有平面设计。 在2Rx4配置中，半导体元件在模块板的上侧布置成两行，并且半导体存储器组件同样在模块板的下侧上排列成两排。 与“堆叠DRAM”设计相反，根据平面设计的半导体器件只包含一个存储器芯片。 通过使用命令地址总线和片上终端总线的并行路由，地址，时钟和控制总线可以根据负载进行调整，从而尽可能避免不同总线上的不同信号传播时间 程度。

公开(公告)号：US20070033490A1

公开(公告)日：2007-02-08

申请号：US11488919

申请日：2006-07-19

Applicant: Karl-Heinz Moosrainer ,  Srdjan Djordjevic ,  Michael Bestele

Inventor： Karl-Heinz Moosrainer ,  Srdjan Djordjevic ,  Michael Bestele

IPC: G11C29/00

CPC classification number: G11C5/025 ,  G06F11/1044 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  Y02P70/611

Abstract: A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board alongside the rows of the memory chips. A control bus connects the ECC memory chips and also the memory chips to the control chip. In a region remote from the control chip, the control bus branches in a contact-making hole into a first partial bus, to which a first group of memory chips are connected, and a second partial bus, to which a second group of memory chips are connected. The ECC memory chips are likewise connected to the control bus via the contact-making hole. Since the ECC memory chips are not arranged directly under the control chip, a bus branch directed backward is not required. As a result, space considerations on the module circuit board are eased and signal integrity on the control buses is improved.

Abstract translation: 半导体存储器模块包括用于驱动ECC存储器芯片和另外的存储器芯片的控制芯片。 存储芯片在模块电路板的上侧和下侧布置成两列。 ECC存储器芯片沿着存储器芯片的行排列在模块电路板的中央。 控制总线将ECC存储器芯片以及存储器芯片连接到控制芯片。 在远离控制芯片的区域中，控制总线将接触孔分支到连接有第一组存储器芯片的第一部分总线和第二部分总线，第二组存储器芯片 被连接。 ECC存储器芯片同样通过接触孔连接到控制总线。 由于ECC存储器芯片不直接布置在控制芯片的下方，所以不需要向后指向的总线分支。 结果，模块电路板上的空间考虑被减轻，并且控制总线上的信号完整性得到改善。

公开(公告)号：US07646650B2

公开(公告)日：2010-01-12

申请号：US11368267

申请日：2006-03-03

Applicant: Georg Braun ,  Srdjan Djordjevic ,  Andreas Jakobs

Inventor： Georg Braun ,  Srdjan Djordjevic ,  Andreas Jakobs

IPC: G11C7/10

CPC classification number: G11C5/063 ,  G06F13/1689 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/109

Abstract: A buffer component for a memory module having a plurality of memory components includes item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.

Abstract translation: 具有多个存储器组件的存储器模块的缓冲器组件包括根据数据传输协议的访问信息项，取决于访问信息的地址，时钟，控制和命令信号，用于驱动时钟信号的第二数据接口 以及根据信令协议对多个存储器组件的地址和命令信号以及用于将控制信号驱动到一组多个存储器组件，其中存储器组件的激活和地址和命令信号的接受是 以取决于控制信号的方式实现;以及控制单元，其在时钟信号的第一时钟周期期间将地址和命令信号施加到多个存储器组件，并施加用于激活多个存储器的组的控制信号 当地址和命令信号时，要激活的多个存储器组件的组件的组件 存在于时钟信号的随后的第二时钟周期中，由此存在的地址和命令信号被接收到多个存储器组件的组中。

公开(公告)号：US20090141581A1

公开(公告)日：2009-06-04

申请号：US11948704

申请日：2007-11-30

Applicant: Srdjan Djordjevic

Inventor： Srdjan Djordjevic

IPC: G11C8/00

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A semiconductor memory arrangement includes a control device with a first port and a second port, the first and second port being adapted to receive command and address signals, a first buffer device being coupled to the first port, a second buffer device being coupled to the second port and a plurality of memory units at least including a first group of memory units and a second group of memory units.

Abstract translation: 半导体存储器装置包括具有第一端口和第二端口的控制装置，第一和第二端口适于接收命令和地址信号，耦合到第一端口的第一缓冲装置，耦合到第一端口的第二缓冲装置， 第二端口和至少包括第一组存储器单元和第二组存储器单元的多个存储器单元。

公开(公告)号：US20080250292A1

公开(公告)日：2008-10-09

申请号：US11697792

申请日：2007-04-09

Applicant: Srdjan Djordjevic

Inventor： Srdjan Djordjevic

IPC: G06F11/00

CPC classification number: G06F11/1044

Abstract: A memory module includes a plurality of memory devices and a stacked error correction code memory device. The plurality of memory devices includes one or more memory chips arranged in a plurality of ranks. The stacked error correction code memory device includes a plurality of error correction code memory chips. The number of error correction code memory chips is at least one more than the number of the one or more memory chips. Each of the error correction code memory chips are arranged together with the memory chips of one of the ranks.

Abstract translation: 存储器模块包括多个存储器件和堆叠的纠错码存储器件。 多个存储器件包括以多个排列排列的一个或多个存储器芯片。 堆叠式纠错码存储装置包括多个纠错码存储芯片。 纠错码存储器芯片的数量比一个或多个存储器芯片的数量多至少一个。 每个纠错码存储器芯片与其中一个等级的存储器芯片一起布置。

公开(公告)号：US20060255459A1

公开(公告)日：2006-11-16

申请号：US11126408

申请日：2005-05-11

Applicant: Simon Muff ,  Srdjan Djordjevic ,  Holger Schroeter ,  Siva RaghuRam

Inventor： Simon Muff ,  Srdjan Djordjevic ,  Holger Schroeter ,  Siva RaghuRam

IPC: H01L23/48

CPC classification number: G11C5/02 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01068 ,  H01L2924/3025 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stacked semiconductor memory device includes memory device contacts to externally connect the stacked semiconductor memory device to a printed circuit board. In a dual or quad stack configuration, the stacked semiconductor memory device includes a first package which is stacked above a second package. The first and second packages are preferably designed as FBGA packages, each of them including package contacts. By providing first and second flexible circuit structures to connect the package contacts of the first and second packages to the memory device contacts, a symmetrical stacked package configuration is obtained. This configuration facilitates transmission of signals with improved signal integrity via a bus of the printed circuit board between the stacked semiconductor memory device and a controller chip, even if the frequency of the bus or the load of the stacked semiconductor memory is increased.

Abstract translation: 堆叠的半导体存储器件包括用于将堆叠的半导体存储器件外部连接到印刷电路板的存储器件触点。 在双堆叠或四堆叠配置中，堆叠的半导体存储器件包括堆叠在第二封装之上的第一封装。 第一和第二封装优选地被设计为FBGA封装，其中每个包括封装触点。 通过提供第一和第二柔性电路结构来将第一和第二封装的封装触点连接到存储器件触点，获得了对称的堆叠封装结构。 即使总线的频率或层叠的半导体存储器的负载增加，这种配置便于通过印刷电路板的总线在堆叠的半导体存储器件和控制器芯片之间传输具有改善的信号完整性的信号。

公开(公告)号：US20060171247A1

公开(公告)日：2006-08-03

申请号：US11346570

申请日：2006-02-03

Applicant: Wolfgang Hoppe ,  Srdjan Djordjevic

Inventor： Wolfgang Hoppe ,  Srdjan Djordjevic

IPC: G11C8/00

CPC classification number: G11C5/04

Abstract: A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2R×4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside of the module board. In contrast to a “Stacked DRAM” design, the semiconductor components in accordance with the planar design contain only one memory chip. By using a parallel routing for a command address bus and an on-die termination bus, the address, clock, and control buses can be adapted in terms of load, so that different signal propagation times on the different buses are avoided to the greatest possible extent.

Abstract translation: 例如，形成为FBDIMM存储器模块的半导体存储器模块具有平面设计。 在2Rx4配置中，半导体元件在模块板的上侧布置成两行，并且半导体存储器组件同样在模块板的下侧上排列成两排。 与“堆叠DRAM”设计相反，根据平面设计的半导体器件只包含一个存储器芯片。 通过使用命令地址总线和片上终端总线的并行路由，地址，时钟和控制总线可以根据负载进行调整，从而尽可能避免不同总线上的不同信号传播时间 程度。

公开(公告)号：US20080259670A1

公开(公告)日：2008-10-23

申请号：US12108366

申请日：2008-04-23

Applicant: Srdjan Djordjevic

Inventor： Srdjan Djordjevic

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/12

Abstract: A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of each memory rank, and a selection signal output for the selection signal of each memory rank, the memory elements being arranged in rows on the board and the memory elements of a memory rank extending only over half of the rows.

Abstract translation: 一种存储器模块，具有在板上的板和多个属于不同存储器等级的存储器元件，每个存储器等级可通过相应的选择信号寻址。 存储器模块还包括具有耦合到每个存储器等级的存储器元件的存储器级接口的存储器缓冲器，以及用于每个存储器级别的选择信号的选择信号，存储器元件被布置在板上的行中，并且存储器 存储器级别的元素仅延伸超过一半行。