SEMICONDUCTOR DEVICE TESTING
    5.
    发明公开

    公开(公告)号:US20240142512A1

    公开(公告)日:2024-05-02

    申请号:US17978170

    申请日:2022-10-31

    CPC classification number: G01R31/2656 G01R31/2601

    Abstract: A semiconductor device testing system, with a platform for supporting a semiconductor substrate, a light emitting system directed toward the platform, a controller, coupled to the light emitting system and adapted to selectively alter an operational parameter of the light emitting system, and a tester configured to characterize an electrical parameter of an electrical device formed in or over the semiconductor substrate while the electrical device is illuminated by one or more wavelengths of light emitted by the light emitting system under direction of the controller.

    REDUCED ESR IN TRENCH CAPACITOR
    7.
    发明申请

    公开(公告)号:US20220406885A1

    公开(公告)日:2022-12-22

    申请号:US17489199

    申请日:2021-09-29

    Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

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