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公开(公告)号:US11888021B2
公开(公告)日:2024-01-30
申请号:US17489199
申请日:2021-09-29
Applicant: Texas Instruments Incorporated
Inventor: Jing Hu , Zhi Peng Feng , Chao Zuo , Dongsheng Liu , Yunlong Liu , Manoj K Jain , Shengpin Yang
IPC: H01L21/762 , H01L49/02 , H01L21/324 , H01L21/225 , H01L21/74 , H01L29/94 , H01L21/3215
CPC classification number: H01L28/87 , H01L21/2253 , H01L21/324 , H01L21/32155 , H01L21/743 , H01L21/76237 , H01L28/40 , H01L29/945
Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.
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公开(公告)号:US12080755B2
公开(公告)日:2024-09-03
申请号:US17512484
申请日:2021-10-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Furen Lin , Yunlong Liu , Zhi Peng Feng , Rui Liu , Rui Song , Manoj K Jain
IPC: H01L23/522 , H01L21/768 , H01L23/495 , H01L27/08 , H01L29/66 , H01L49/02
Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.
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公开(公告)号:US11322594B2
公开(公告)日:2022-05-03
申请号:US17134706
申请日:2020-12-28
Applicant: Texas Instruments Incorporated
Inventor: Fei Ma , Ya ping Chen , Yunlong Liu , Hong Yang , Shengpin Yang , Baoqiang Niu , Rui Liu , Zhi Peng Feng , Seetharaman Sridhar , Sunglyong Kim
IPC: H01L29/40 , H01L29/78 , H01L29/66 , H01L21/765 , H01L29/423 , H01L27/24 , H01L21/8234
Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.
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公开(公告)号:US20240395854A1
公开(公告)日:2024-11-28
申请号:US18795747
申请日:2024-08-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Furen Lin , Yunlong Liu , Zhi Peng Feng , Rui Liu , Rui Song , Manoj K Jain
IPC: H01G4/30
Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.
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公开(公告)号:US20240142512A1
公开(公告)日:2024-05-02
申请号:US17978170
申请日:2022-10-31
Applicant: Texas Instruments Incorporated
Inventor: Zhi Peng Feng , Ren Hui Fan , Alfred Griffin , He Lin
IPC: G01R31/265 , G01R31/26
CPC classification number: G01R31/2656 , G01R31/2601
Abstract: A semiconductor device testing system, with a platform for supporting a semiconductor substrate, a light emitting system directed toward the platform, a controller, coupled to the light emitting system and adapted to selectively alter an operational parameter of the light emitting system, and a tester configured to characterize an electrical parameter of an electrical device formed in or over the semiconductor substrate while the electrical device is illuminated by one or more wavelengths of light emitted by the light emitting system under direction of the controller.
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公开(公告)号:US20220416014A1
公开(公告)日:2022-12-29
申请号:US17512484
申请日:2021-10-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Furen Lin , Yunlong Liu , Zhi Peng Feng , Rui Liu , Rui Song , Manoj K. Jain
IPC: H01L49/02
Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.
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公开(公告)号:US20220406885A1
公开(公告)日:2022-12-22
申请号:US17489199
申请日:2021-09-29
Applicant: Texas Instruments Incorporated
Inventor: Jing Hu , Zhi Peng Feng , Chao Zuo , Dongsheng Liu , Yunlong Liu , Manoj K. Jain , Shengpin Yang
IPC: H01L49/02
Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.
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