公开(公告)号：US20120139010A1

公开(公告)日：2012-06-07

申请号：US13310896

申请日：2011-12-05

Applicant: TSUTOMU TAKEDA

Inventor： TSUTOMU TAKEDA

IPC: H01L29/772 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1515 ,  H01L2924/15311

Abstract: An interposer includes a substrate includes a plurality of penetrating electrodes, and a wiring portion formed on the substrate, in which the wiring portion includes a wiring layer electrically connected to the penetrating electrodes and an insulating layer covering the wiring layer. The interposer includes a plurality of first UBM structures provided at a side opposite the substrate of the wiring portion, in which the first UBM structures are electrically connected to the wiring layer. The interposer includes a plurality of bumps provided at the side opposite the wiring portion of the substrate, in which the plurality of bumps is electrically connected to each of the penetrating electrodes via a plurality of second UBM structures.

Abstract translation: 插入件包括：基板，包括多个穿透电极;以及布线部，形成在所述基板上，所述布线部分包括与所述穿透电极电连接的布线层和覆盖所述布线层的绝缘层。 插入器包括多个第一UBM结构，其设置在与布线部分的基板相对的一侧，其中第一UBM结构电连接到布线层。 插入器包括设置在与基板的布线部分相对的一侧的多个凸块，其中多个凸块经由多个第二UBM结构电连接到每个穿透电极。

公开(公告)号：US20110226516A1

公开(公告)日：2011-09-22

申请号：US13024897

申请日：2011-02-10

Applicant: TSUTOMU TAKEDA

Inventor： TSUTOMU TAKEDA

IPC: H05K1/16

CPC classification number: H05K1/0251 ,  H01L2924/15311 ,  H01L2924/19051 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09809 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/0207 ,  H05K2203/1572

Abstract: A wiring board includes at least one signal layer, at least one ground layer, at least one power plane, at least one power supply via that electrically conducts wiring over one substrate surface where a semiconductor device chip is mounted, wiring over another substrate surface, and the power plane, and signal wiring for performing signal transmission between a plurality of semiconductor device chips. The power plane is placed to the one substrate surface side than the signal wiring. The power supply via is composed of a large diameter aperture and a small diameter aperture. The large diameter aperture has a relatively large diameter and is formed from the one substrate surface to the power plane, and the small diameter aperture has a relatively small diameter and is formed from the power plane to the other substrate surface.

Abstract translation: 布线板包括至少一个信号层，至少一个接地层，至少一个电力平面，至少一个电源通孔，该电源通过一个衬底表面上电导线，半导体器件芯片安装在一个衬底表面上，在另一个衬底表面上布线， 以及用于在多个半导体器件芯片之间进行信号传输的信号布线。 电源平面被放置在与信号布线相对的一个基板表面侧。 电源通孔由大直径孔径和小直径孔径组成。 大直径孔径具有相对大的直径，并且由一个基板表面到动力平面形成，并且小直径孔径具有相对较小的直径并且从动力平面形成到另一个基底表面。

公开(公告)号：US20080218985A1

公开(公告)日：2008-09-11

申请号：US12042484

申请日：2008-03-05

Applicant: TSUTOMU TAKEDA

Inventor： TSUTOMU TAKEDA

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/42 ,  H05K3/10

CPC classification number: H05K1/115 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/112 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/09809 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A printed circuit board is provided which is capable of shortening intervals among core layer vias and suppressing high impedance. After the core layer vias each having a cylindrical conducting layer are formed so that conducting portions come into contact with one another, a punching process is performed along a symmetric axis of each of four core layer vias so that a through-hole of a specified diameter passes through a core board to form the core layer vias separated from one another and the through-hole is filled with an insulator and a punching process is performed along a central axis of the through-hole filled with the insulator so as to pass through the core board to form the through-hole having a diameter being shorter than that of the through-hole and the conducting layer is formed on an inside wall of the through-hole to form the core layer via.

Abstract translation: 提供一种印刷电路板，其能够缩短芯层通孔之间的间隔并抑制高阻抗。 在形成具有圆柱形导电层的芯层通孔之后，导电部分彼此接触，沿着四个芯层通孔中的每一个的对称轴进行冲压加工，使得具有特定直径的通孔 通过芯板形成彼此分离的芯层通孔，并且通孔填充有绝缘体，并且沿着填充有绝缘体的通孔的中心轴进行冲压加工，以便穿过绝缘体 形成直径比通孔的直径短的通孔，并且在通孔的内壁上形成导电层以形成芯层通孔。