公开(公告)号：US09818607B2

公开(公告)日：2017-11-14

申请号：US14745752

申请日：2015-06-22

Applicant: The Hong Kong University of Science and Technology

Inventor： Hoi Sing Kwok ,  Man Wong ,  Rongsheng Chen ,  Meng Zhang ,  Wei Zhou

IPC: H01L29/04 ,  H01L21/02 ,  H01L29/786 ,  H01L29/16 ,  H01L29/32

CPC classification number: H01L21/02672 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L29/04 ,  H01L29/16 ,  H01L29/32 ,  H01L29/786

Abstract: Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.

公开(公告)号：US10381564B2

公开(公告)日：2019-08-13

申请号：US15753519

申请日：2016-08-17

Applicant: The Hong Kong University of Science and Technology

Inventor： Hoi Sing Kwok ,  Guijun Li ,  Yeuk Lung Jacob Ho ,  Man Wong

IPC: H01L51/00 ,  H01L51/42 ,  H01G9/00 ,  H01G9/20 ,  H01L51/44 ,  H01L51/50 ,  H01L51/52

Abstract: A method of fabricating a hybrid organic-inorganic halide perovskite film includes depositing a precursor layer onto a substrate, the precursor layer comprising metal halide, placing an organic source-material layer onto a boat, the organic source-material layer comprising an organic cation, and annealing the precursor layer and the organic source-material layer in a vacuum chamber enclosed in a constrained volume.

公开(公告)号：US10032924B2

公开(公告)日：2018-07-24

申请号：US14671055

申请日：2015-03-27

Applicant: The Hong Kong University of Science and Technology

Inventor： Lei Lu ,  Man Wong ,  Hoi Sing Kwok

IPC: H01L29/786 ,  H01L21/477 ,  H01L21/465 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

Abstract: An apparatus is provided that includes a substrate and source and drain regions within an annealed active layer having resulted from an annealing of an active layer comprising metal-oxide and formed on the substrate, and an impermeable layer over the source and drain regions of the annealed active layer, wherein the annealing resulting in the annealed active layer was performed with the impermeable layer over portions of the active layer corresponding to the source and drain regions, thereby resulting in a reduction of a resistivity of the source and drain regions of the annealed active layer relative to the active layer. In another aspect, a junctionless transistor is provided wherein the entire active area has a low resistivity based on annealing of an active layer including metal oxide while uncovered or at least partially covered with layers of various gas permeability under oxidizing or non-oxidizing conditions.

公开(公告)号：US20180240821A1

公开(公告)日：2018-08-23

申请号：US15899995

申请日：2018-02-20

Applicant: The Hong Kong University of Science and Technology

Inventor： Lei Lu ,  Wei Zhou ,  Man Wong ,  Hoi Sing Kwok

IPC: H01L27/12

CPC classification number: H01L27/1251 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/266 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the active layers. In one or more embodiments, an apparatus is provided that comprises a first transistor comprising a silicon active layer, and a second transistor comprising a metal oxide active layer. The second transistor is vertically stacked on the first transistor, and the first transistor and the second transistor share a gate electrode formed between the silicon active layer and the metal oxide active layer. With these embodiments, the gate electrode corresponds to a top gate of the first transistor and a bottom gate of the second transistor.

公开(公告)号：US09960281B2

公开(公告)日：2018-05-01

申请号：US14617181

申请日：2015-02-09

Applicant: The Hong Kong University of Science and Technology

Inventor： Lei Lu ,  Man Wong ,  Hoi Sing Kwok

IPC: H01L29/786 ,  H01L21/426 ,  H01L27/12 ,  H01L29/66 ,  H01L29/24 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/425 ,  H01L21/426 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618

Abstract: Thin film transistors are provided that include a metal oxide active layer with source and drain regions having a reduced resistivity relative to the metal oxide based on doping of the source and drain regions at room temperature. In an aspect, a transistor structure is provided, that includes a substrate, and source and drain regions within a doped active layer having resulted from doping of an active layer comprising metal-oxide and formed on the substrate, wherein the doped active layer was doped at room temperature and without thermal annealing, thereby resulting in a reduction of a resistivity of the source and drain regions of the doped active layer relative to the active layer prior to the doping. In an aspect, the source and drain regions have a resistivity of about 10.0 mΩ·cm after being doped with stable ions and without subsequent activation of the ions via annealing.

公开(公告)号：US09214568B2

公开(公告)日：2015-12-15

申请号：US14104762

申请日：2013-12-12

Applicant: The Hong Kong University of Science and Technology

Inventor： Hoi Sing Kwok ,  Meng Zhang ,  Shuming Chen ,  Wei Zhou ,  Man Wong

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/6675 ,  H01L29/78675

Abstract: A thin film transistor includes: a source region; a drain region; and a polycrystalline thin film active channel region connected to the source region and the drain region, the active channel region comprising grains and being doped with a two-dimensional pattern comprising a plurality of doped regions, the plurality of doped regions each comprising at least portions of a plurality of the grains and at least one grain boundary.

Abstract translation: 薄膜晶体管包括：源极区; 漏区; 以及连接到源区和漏区的多晶薄膜有源沟道区，所述有源沟道区包含晶粒并掺杂有包括多个掺杂区的二维图案，所述多个掺杂区各自包括至少部分 的多个晶粒和至少一个晶界。

公开(公告)号：US20180315860A1

公开(公告)日：2018-11-01

申请号：US15581322

申请日：2017-04-28

Applicant: The Hong Kong University of Science and Technology

Inventor： Lei Lu ,  Zhi He Xia ,  Jia Peng Li ,  Man Wong ,  Hoi Sing Kwok

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L21/477 ,  H01L21/768

Abstract: Aspects describe a vertical metal-oxide thin-film transistor with multiple-junction channel and a method to fabricate the same. In one example, the vertical transistor comprises a substrate, an interconnecting electrode and source and drain electrodes separated by a spacer. The vertical transistor also includes a metal oxide active layer formed over the interconnecting electrode and the source and drain electrodes and adjacent to the interconnecting electrode, the spacer, and the source and drain electrodes. Further, the vertical transistor includes a gate stack adjacent to the metal oxide active layer and a multiple-junction channel region provided within the metal oxide active layer adjacent to the gate stack.

公开(公告)号：US20160020095A1

公开(公告)日：2016-01-21

申请号：US14745752

申请日：2015-06-22

Applicant: The Hong Kong University of Science and Technology

Inventor： Hoi Sing Kwok ,  Man Wong ,  Rongsheng Chen ,  Meng Zhang ,  Wei Zhou

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/32 ,  H01L29/786 ,  H01L29/16

CPC classification number: H01L21/02672 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L29/04 ,  H01L29/16 ,  H01L29/32 ,  H01L29/786

Abstract: Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.

Abstract translation: 提供了用于形成薄膜晶体管的技术，该薄膜晶体管具有通过在氧化气氛中的非晶硅的金属诱导结晶（MIC）形成的多晶硅有源层。 在一方面，提供了一种晶体管器件，其包括形成在衬底上的源极区域和漏极区域以及形成在衬底上并且电连接源极区域和漏极区域的有源沟道区域。 有源沟道区形成有由在基板上形成的非晶硅层退火而形成的多晶硅层，其上形成有金属层，其中非晶硅层的退火至少部分地在氧化气氛中进行，由此 导致非晶硅层的结晶以形成多晶硅层。

公开(公告)号：US08716050B2

公开(公告)日：2014-05-06

申请号：US13721496

申请日：2012-12-20

Applicant: The Hong Kong University of Science and Technology

Inventor： Man Wong ,  Fan Zeng

IPC: H01L21/00 ,  H01L29/82

CPC classification number: H01L21/461 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00822 ,  B01J2219/00828 ,  B01J2219/00837 ,  B01J2219/0086 ,  B01L3/502707 ,  B01L2300/0816 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00071 ,  B81C2201/0116 ,  B81C2201/0178 ,  H01L29/16

Abstract: Described herein is a microchannel that is formed beneath and parallel to a surface of a silicon substrate. Silicon migration technology is utilized to form a microchannel that is buried beneath the surface of the silicon substrate. Etching opens at least one end of the microchannel. Oxidization is utilized through the open end of the microchannel to facilitate a controlled diameter of the microchannel.

Abstract translation: 这里描述的是形成在硅衬底的表面下方并平行于其的表面的微通道。 利用硅迁移技术形成埋在硅衬底表面下方的微通道。 蚀刻打开微通道的至少一端。 通过微通道的开口端利用氧化，以促进微通道的受控直径。