公开(公告)号：US09256405B1

公开(公告)日：2016-02-09

申请号：US14185510

申请日：2014-02-20

Applicant: The MathWorks, Inc.

Inventor： Sankalp S. Modi ,  Wang Chen ,  Zhihong Zhao ,  Partha Biswas

IPC: G06F9/44

CPC classification number: G06F8/35

Abstract: A device is configured to receive optimization information associated with a model, determine an amount of delay to be inserted into the model, and determine a sampling factor by which a first data rate associated with a signal is to be modified into a second data rate. The device is configured to determine a region of interest, insert an upsampling block that upsamples the signal entering the region of interest based on the sampling factor, and insert a downsampling block, associated with a unit of delay, which downsamples the signal exiting the region of interest based on the sampling factor. The device is configured to convert the unit of delay into a fast delay block, corresponding to the amount of delay, and insert the fast delay block in the region of interest. The device is configured to generate code associated with the model, and provide the code.

Abstract translation: 设备被配置为接收与模型相关联的优化信息，确定要插入模型的延迟量，以及确定与信号相关联的第一数据速率将被修改为第二数据速率的采样因子。 该设备被配置为确定感兴趣的区域，插入基于采样因子对进入感兴趣区域的信号进行上采样的上采样块，并插入与延迟单元相关联的下采样块，其对离开该区域的信号进行下采样 基于抽样因子的兴趣。 该设备被配置为将延迟单元转换成对应于延迟量的快速延迟块，并将快速延迟块插入到感兴趣的区域中。 该设备被配置为生成与模型相关联的代码，并提供代码。

公开(公告)号：US10095814B1

公开(公告)日：2018-10-09

申请号：US14185514

申请日：2014-02-20

Applicant: The MathWorks, Inc.

Inventor： Partha Biswas ,  Yongfeng Gu ,  Zhihong Zhao

IPC: G06F17/50

Abstract: A device is configured to receive delay information associated with a model including a set of model elements and one or more delay elements. The delay information may identify a model element, of the set of model elements, and a quantity of delay to be associated with the model element. The model may be associated with a total quantity of delay. The device is configured to determine accumulated delay information based on the model, and to determine a set of retiming values associated with the set of model elements. The device is configured to redistribute the one or more delay elements associated with the model, based on the set of retiming values, to satisfy the quantity of delay to be associated with the model element, and to maintain the total quantity of delay associated with the model. The device is configured to provide the redistributed model.

公开(公告)号：US08904367B1

公开(公告)日：2014-12-02

申请号：US13803689

申请日：2013-03-14

Applicant: The MathWorks, Inc.

Inventor： Partha Biswas ,  Vijaya Raghavan ,  Zhihong Zhao

IPC: G06F9/45

CPC classification number: G06F9/44557 ,  G06F8/441 ,  G06F8/4451 ,  G06F17/505 ,  G06F17/5072

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract translation: 系统和方法将管道自动插入到高级程序规范中。 中间表示（IR）构建器基于高级程序规范创建一个或多个图形或树。 调度器迭代地应用有界调度算法来产生用于IR的执行调度，使给定数量的流水线级的总体执行时间最小化。 硬件描述语言（HDL）代码生成器可以利用流水线计划的IR来产生对应于高级程序规范的优化的HDL代码。 显示管道插入位置的高级程序规范的注释版本可以被显示，允许额外的设计探索。