公开(公告)号：US20190302242A1

公开(公告)日：2019-10-03

申请号：US15941284

申请日：2018-03-30

Applicant: Tower Semiconductor Ltd.

Inventor： Amos Fenigstein ,  Dmitry Dain ,  Tomer Leitner

IPC: G01S7/486 ,  H01L31/02 ,  H01L31/107 ,  G01S7/484 ,  G01S17/06 ,  G01J1/46

Abstract: A sensor circuit having a Single Photon Avalanche Diode (SPAD) and an active quenching circuit including a quenching transistor controlled by a one-shot (or similar) circuit is disclosed. The quenching transistor applies a reverse-bias voltage level on the cathode of the SPAD. During photon detection events, pulses generated by the SPAD's avalanche breakdown trigger the one-shot circuit to de-actuate the quenching transistor, allowing the cathode potential to drop below the SPAD's breakdown voltage. After a delay period, which is defined by the one-shot's configuration, allows reliable completion of the avalanche breakdown process, the one-shot circuit re-actuates the quenching transistor such that the SPAD's cathode is refreshed to the reverse-bias voltage level. The one-shot circuit is optionally coupled by way of capacitors to the SPAD and the quenching transistor to facilitate implementation using standard CMOS elements. The sensor is suitable for use in a LIDAR system.

公开(公告)号：US20170323912A1

公开(公告)日：2017-11-09

申请号：US15658328

申请日：2017-07-24

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein ,  Yakov Roizin ,  Avi Strum

IPC: H01L27/146 ,  H04N5/353 ,  H04N5/3745

CPC classification number: H01L27/1461 ,  H01L27/14609 ,  H01L27/14614 ,  H01L27/14623 ,  H01L27/14643 ,  H04N5/3532 ,  H04N5/3745 ,  H04N5/37452 ,  H04N5/3765

Abstract: A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

公开(公告)号：US09210345B2

公开(公告)日：2015-12-08

申请号：US13764776

申请日：2013-02-11

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein

IPC: H04N5/357 ,  H04N5/3745 ,  H04N5/353

CPC classification number: H04N5/3575 ,  H04N5/3532 ,  H04N5/37452 ,  H04N5/37457

Abstract: A method for operating a global shutter image sensor includes performing both a global shutter (image capture) operation and a rolling shutter (readout) operation. During the global shutter operation, image information (charges) are captured by photodiodes in every pixel, and then simultaneously transferred to charge coupled gate (CCG) devices provided in each pixel. The rolling shutter operation includes performing multiple correlated double sampling (CDS) readout phases utilizing readout circuits that are shared by groups of pixels (e.g., four pixels share each readout circuit) having CCG devices connected in a chain. After resetting a floating diffusion in the readout circuit, a first captured charge is transferred to floating diffusion for readout, and the remaining charges are shifted along the CCG chain. The remaining CCG devices are then sequentially read out by repeating the read-and-shift operation. The readout operation is then repeated for each row of pixel groups.

Abstract translation: 用于操作全局快门图像传感器的方法包括执行全局快门（图像拍摄）操作和滚动快门（读出）操作。 在全局快门操作期间，每个像素中的光电二极管拍摄图像信息（电荷），然后同时传送到每个像素中提供的电荷耦合栅极（CCG）装置。 滚动快门操作包括利用由链中连接的CCG设备的像素组（例如，四个像素共享每个读出电路）共享的读出电路来执行多个相关双采样（CDS）读出阶段。 在读出电路中重置浮动扩散之后，将第一捕获电荷转移到浮动扩散用于读出，并且剩余电荷沿着CCG链移动。 然后通过重复读取和移位操作来顺序读出剩余的CCG设备。 然后对每行像素组重复读出操作。

公开(公告)号：US20140226046A1

公开(公告)日：2014-08-14

申请号：US13764766

申请日：2013-02-11

Applicant: TOWER SEMICONDUCTOR LTD.

Inventor： Assaf Lahav ,  Amos Fenigstein

IPC: H04N5/335

CPC classification number: H04N5/37457 ,  H04N5/353

Abstract: A global shutter image sensor includes an array of pixel groups arranged in rows and columns, each pixel group including four pixels and a shared readout circuit having a floating diffusion. Each pixel includes a photodiode, a transfer gate and a charge coupled gate (CCG) device. The CCG devices are coupled in series with the floating diffusion of the shared readout circuit. Control circuitry controls the image sensor such that all of the pixels simultaneously capture image information (charges) and then transfer the captured charges to the CCG devices during a global shutter operation. The control circuit then controls the CCG devices to act as a shift register that transfers the captured charges to the floating diffusion during sequential correlated double sampling readout phases. The readout circuit includes a shared reset transistor, a source-follower and row select transistor, and each pixel group is controlled by eight or fewer control signals.

Abstract translation: 全局快门图像传感器包括排列成行和列的像素组的阵列，每个像素组包括四个像素，以及具有浮动扩散的共享读出电路。 每个像素包括光电二极管，传输门和电荷耦合栅极（CCG）器件。 CCG器件与共享读出电路的浮动扩散串联耦合。 控制电路控制图像传感器，使得所有像素同时捕获图像信息（电荷），然后在全局快门操作期间将捕获的电荷传送到CCG装置。 然后，控制电路控制CCG器件作为移位寄存器，以在顺序相关的双取样读出阶段将捕获的电荷传送到浮动扩散。 读出电路包括共享复位晶体管，源极跟随器和行选择晶体管，并且每个像素组由八个或更少的控制信号控制。

公开(公告)号：US20160286151A1

公开(公告)日：2016-09-29

申请号：US14665803

申请日：2015-03-23

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein ,  Yakov Roizin ,  Avi Strum

IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/376

CPC classification number: H04N5/37452 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14614 ,  H01L27/14623 ,  H01L27/14643 ,  H04N5/3765

Abstract: A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Abstract translation: 全局快门（GS）图像传感器像素包括通过第一传输门晶体管连接到存储器节点的钉扎光电二极管和通过第二传输栅极晶体管连接到存储器节点的浮动扩散。 存储节点包括设置在第一传输栅极晶体管下方的掩埋沟道部分和设置在第一和第二传输栅极晶体管之间的连续的钉扎二极管部分，其中两个存储器节点部分具有不同的掺杂水平，使得本征横向电场驱动电子 从埋入通道部分进入固定二极管部分。 浮动扩散节点类似地包括设置在第二传输栅极晶体管下方的掩埋沟道部分和连续的钉扎二极管部分，其产生将电子驱动到浮动扩散的钉扎二极管部分的第二本征横向电场。 公开了一种有助于低噪声CDS读出的6T CMOS像素。

公开(公告)号：US09356169B2

公开(公告)日：2016-05-31

申请号：US14791657

申请日：2015-07-06

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein

IPC: H01L31/062 ,  H01L31/0352 ,  H01L27/146

CPC classification number: H01L31/035272 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.

Abstract translation: 一些演示实施例包括背面照明（BSI）互补金属氧化物半导体（CMOS）像素阵列的装置和/或方法。 例如，BSI CMOS像素阵列可以包括多个像素，多个像素中的像素可以包括一个或多个金属氧化物半导体（MOS）晶体管，其包括一个或多个阱区，一个或多个 更好的区域包括N阱（NW）区域或P阱（PW）区域; 光电二极管 包括吸收区域和收集区域的外延（epi）层，吸收进入的光子并响应于吸收的光子产生电子的吸收区域，以及将吸收区域连接到光电二极管以从吸收区域提供电子的收集区域 到光电二极管; 以及将吸收区域与一个或多个阱区域分开的阻挡层。

公开(公告)号：US20160133666A1

公开(公告)日：2016-05-12

申请号：US14536649

申请日：2014-11-09

Applicant: Tower Semiconductor Ltd.

Inventor： Amos Fenigstein ,  Yakov Roizin ,  Avi Strum

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/1462 ,  H01L27/14689 ,  H01L27/14692 ,  H01L27/14698

Abstract: A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures.

Abstract translation: 一种制造图像传感器和其他半导体IC的方法，其控制在后端处理期间产生的氢气量。 后端处理包括在前端处理完成之后形成多个金属化层（即，在形成预金属电介质之后），其中每个金属化层包括图案化的铝结构，层间电介质（ILD）层，包括基于TEOS的 形成在图案化铝结构上的氧化物。 在至少一个ILD层上形成包含诸如硅烷氧化物（即通过硅烷CVD工艺生成的SiO 2）的低含水量氧化物的盖层。 在铝过蚀刻期间，通过将下面的ILD材料与等离子体环境隔离，盖层用作随后形成的下一个金属化层的金属层的蚀刻停止层，这显着地减少了氢的生成和迁移到前端 结构。

公开(公告)号：US20160005896A1

公开(公告)日：2016-01-07

申请号：US14791657

申请日：2015-07-06

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein

IPC: H01L31/0352 ,  H01L27/146

CPC classification number: H01L31/035272 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.

Abstract translation: 一些演示实施例包括背面照明（BSI）互补金属氧化物半导体（CMOS）像素阵列的装置和/或方法。 例如，BSI CMOS像素阵列可以包括多个像素，多个像素中的像素可以包括一个或多个金属氧化物半导体（MOS）晶体管，其包括一个或多个阱区，一个或多个 更好的区域包括N阱（NW）区域或P阱（PW）区域; 光电二极管 包括吸收区域和收集区域的外延（epi）层，吸收进入的光子并响应于吸收的光子产生电子的吸收区域，以及将吸收区域连接到光电二极管以从吸收区域提供电子的收集区域 到光电二极管; 以及将吸收区域与一个或多个阱区域分开的阻挡层。

公开(公告)号：US09160956B2

公开(公告)日：2015-10-13

申请号：US13764766

申请日：2013-02-11

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein

IPC: H04N5/3745 ,  H04N5/353

CPC classification number: H04N5/37457 ,  H04N5/353

Abstract: A global shutter image sensor includes an array of pixel groups arranged in rows and columns, each pixel group including four pixels and a shared readout circuit having a floating diffusion. Each pixel includes a photodiode, a transfer gate and a charge coupled gate (CCG) device. The CCG devices are coupled in series with the floating diffusion of the shared readout circuit. Control circuitry controls the image sensor such that all of the pixels simultaneously capture image information (charges) and then transfer the captured charges to the CCG devices during a global shutter operation. The control circuit then controls the CCG devices to act as a shift register that transfers the captured charges to the floating diffusion during sequential correlated double sampling readout phases. The readout circuit includes a shared reset transistor, a source-follower and row select transistor, and each pixel group is controlled by eight or fewer control signals.

Abstract translation: 全局快门图像传感器包括排列成行和列的像素组的阵列，每个像素组包括四个像素，以及具有浮动扩散的共享读出电路。 每个像素包括光电二极管，传输门和电荷耦合栅极（CCG）器件。 CCG器件与共享读出电路的浮动扩散串联耦合。 控制电路控制图像传感器，使得所有像素同时捕获图像信息（电荷），然后在全局快门操作期间将捕获的电荷传送到CCG装置。 然后，控制电路控制CCG器件作为移位寄存器，以在顺序相关的双取样读出阶段将捕获的电荷传送到浮动扩散。 读出电路包括共享复位晶体管，源极跟随器和行选择晶体管，并且每个像素组由八个或更少的控制信号控制。

公开(公告)号：US11592584B1

公开(公告)日：2023-02-28

申请号：US17444562

申请日：2021-08-05

Applicant: Tower Semiconductor Ltd.

Inventor： Amos Fenigstein

IPC: G01T1/24 ,  H01L27/144

Abstract: There may be provided a radiation sensor, that may include multiple semiconductor regions that form a sensing PN junction and a draining PN junction that is located below the sensing PN junction; a bias circuit that is configured to (i) bias the sensing PN junction to maintain a sensing PN junction depletion region of a fixed size during a first sensing period and during a second sensing period, and (i) bias the draining PN junction to form a draining PN junction depletion region of a first size during the first sensing period and of a second size during the second sensing period; and an output circuit that is configured to generate a first output signal that represent sensed radiation out of radiation that impinged on the radiation sensor during the first sensing period, and to generate a second output signal that represent sensed radiation out of radiation impinged on the radiation sensor during the second sensing period.