公开(公告)号：US20170323830A1

公开(公告)日：2017-11-09

申请号：US15476423

申请日：2017-03-31

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan

IPC: H01L21/82 ,  H01L23/498 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522

CPC classification number: H01L21/82 ,  H01L21/311 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/762 ,  H01L23/12 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/538 ,  H05K1/113 ,  H05K3/184 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4661

Abstract: An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

公开(公告)号：US20180209046A1

公开(公告)日：2018-07-26

申请号：US15878657

申请日：2018-01-24

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan ,  Poh Cheng Ang

IPC: C23C18/16 ,  H01L23/498 ,  C25D5/02 ,  H05K3/18 ,  H05K1/11 ,  H01L21/48 ,  H05K3/46

CPC classification number: C23C18/1653 ,  C23C18/1605 ,  C23C18/1607 ,  C23C18/1657 ,  C25D5/022 ,  H01L21/486 ,  H01L23/49822 ,  H05K1/115 ,  H05K3/184 ,  H05K3/205 ,  H05K3/244 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2201/10378

Abstract: An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

公开(公告)号：US10190218B2

公开(公告)日：2019-01-29

申请号：US15878657

申请日：2018-01-24

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan ,  Poh Cheng Ang

IPC: H01L21/02 ,  H01L23/52 ,  C23C18/16 ,  H01L23/498 ,  C25D5/02 ,  H05K1/11 ,  H01L21/48 ,  H05K3/46 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24

Abstract: An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

公开(公告)号：US20180197754A1

公开(公告)日：2018-07-12

申请号：US15741154

申请日：2015-09-02

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Poh Cheng Ang ,  Linhui Yuan

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/20 ,  H05K1/02

Abstract: The present invention relates to an integrated circuit packaging, comprising: a plurality of electrical circuits using a first patterned conductive layer (103) formed by using a masking material (102); a second patterned conductive layer (105) having disposed on at least one side of the first patterned conductive layer (103); and a first dielectric layer (106) made from a laminating means, wherein the first patterned conductive layer (103) and the second patterned conductive layer (105) are disposed within the first dielectric layer (106), such that at least one side of the first dielectric layer (106) are located at the same plane with the first patterned conductive layer (103),

公开(公告)号：US10424492B2

公开(公告)日：2019-09-24

申请号：US15741154

申请日：2015-09-02

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Poh Cheng Ang ,  Linhui Yuan

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H05K3/20 ,  H01L23/498

Abstract: The present invention relates to an integrated circuit packaging, comprising: a plurality of electrical circuits using a first patterned conductive layer (103) formed by using a masking material (102); a second patterned conductive layer (105) having disposed on at least one side of the first patterned conductive layer (103); and a first dielectric layer (106) made from a laminating means, wherein the first patterned conductive layer (103) and the second patterned conductive layer (105) are disposed within the first dielectric layer (106), such that at least one side of the first dielectric layer (106) are located at the same plane with the first patterned conductive layer (103).

公开(公告)号：US20170323829A1

公开(公告)日：2017-11-09

申请号：US15475956

申请日：2017-03-31

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan

IPC: H01L21/82 ,  H01L23/498 ,  H01L21/762 ,  H01L21/74 ,  H01L21/71 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/82 ,  H01L21/311 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/71 ,  H01L21/743 ,  H01L21/762 ,  H01L23/12 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/522

Abstract: An integrated circuit packaging is described and includes a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein the electrical circuit is formed by using a masking material, and a stud conductive layer disposed on at least one side of the first patterned conductive layer developed by a second layer photo-resist material on the masking material, in which the second layer photo-resist material includes a first line layer with a smaller exposed area than the surface of the conductive layer disposed on one side of the first patterned conductive layer and a second line layer with a larger exposed area than the first line layer disposed on the first layer, such that the exposed area forms an “I” shaped connection of the conductive layer and the stud conductive layer.

公开(公告)号：US20170323826A1

公开(公告)日：2017-11-09

申请号：US15476648

申请日：2017-03-31

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan

IPC: H01L21/768 ,  H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L21/70

Abstract: An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.