公开(公告)号：US20180209046A1

公开(公告)日：2018-07-26

申请号：US15878657

申请日：2018-01-24

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan ,  Poh Cheng Ang

IPC: C23C18/16 ,  H01L23/498 ,  C25D5/02 ,  H05K3/18 ,  H05K1/11 ,  H01L21/48 ,  H05K3/46

CPC classification number: C23C18/1653 ,  C23C18/1605 ,  C23C18/1607 ,  C23C18/1657 ,  C25D5/022 ,  H01L21/486 ,  H01L23/49822 ,  H05K1/115 ,  H05K3/184 ,  H05K3/205 ,  H05K3/244 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2201/10378

Abstract: An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

公开(公告)号：US10190218B2

公开(公告)日：2019-01-29

申请号：US15878657

申请日：2018-01-24

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan ,  Poh Cheng Ang

IPC: H01L21/02 ,  H01L23/52 ,  C23C18/16 ,  H01L23/498 ,  C25D5/02 ,  H05K1/11 ,  H01L21/48 ,  H05K3/46 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24

Abstract: An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

公开(公告)号：US20180197754A1

公开(公告)日：2018-07-12

申请号：US15741154

申请日：2015-09-02

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Poh Cheng Ang ,  Linhui Yuan

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/20 ,  H05K1/02

Abstract: The present invention relates to an integrated circuit packaging, comprising: a plurality of electrical circuits using a first patterned conductive layer (103) formed by using a masking material (102); a second patterned conductive layer (105) having disposed on at least one side of the first patterned conductive layer (103); and a first dielectric layer (106) made from a laminating means, wherein the first patterned conductive layer (103) and the second patterned conductive layer (105) are disposed within the first dielectric layer (106), such that at least one side of the first dielectric layer (106) are located at the same plane with the first patterned conductive layer (103),

公开(公告)号：US10424492B2

公开(公告)日：2019-09-24

申请号：US15741154

申请日：2015-09-02

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Poh Cheng Ang ,  Linhui Yuan

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H05K3/20 ,  H01L23/498

Abstract: The present invention relates to an integrated circuit packaging, comprising: a plurality of electrical circuits using a first patterned conductive layer (103) formed by using a masking material (102); a second patterned conductive layer (105) having disposed on at least one side of the first patterned conductive layer (103); and a first dielectric layer (106) made from a laminating means, wherein the first patterned conductive layer (103) and the second patterned conductive layer (105) are disposed within the first dielectric layer (106), such that at least one side of the first dielectric layer (106) are located at the same plane with the first patterned conductive layer (103).