公开(公告)号：US20210342991A1

公开(公告)日：2021-11-04

申请号：US17244183

申请日：2021-04-29

Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA

Inventor： Ajey Poovannummoottil JACOB ,  John DAMOULAKIS ,  Akhilesh JAISWAL ,  Devanand Krishna SHENOY ,  Andrew RITTENBACH

IPC: G06T7/00 ,  G06T7/30 ,  G06T3/40 ,  G06T11/00 ,  H01J37/28 ,  H01J37/244

Abstract: A method for assuring that integrated circuits are free of malicious circuit insertions and/or IC design modifications through mask swapping/addition is provided. The method includes a step of comparing 3D tomographic images constructed from design GDS to the 3D tomographic images constructed from in-line fab metrology data.