公开(公告)号：US20220028907A1

公开(公告)日：2022-01-27

申请号：US17443380

申请日：2021-07-26

Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA

Inventor： Rehan Rashid KAPADIA ,  Khaled AHMED ,  Frank GREER

IPC: H01L27/146 ,  H01L31/0304 ,  H01L31/18

Abstract: A method for forming a composite substrate containing layers of dissimilar materials is provided. The method includes a step of disposing a release layer over a base substrate where the base substrate is composed of a first material. A template layer is attached to the release layer. Characteristically, the template layer is composed of a second material and adapted to form a compound semiconductor device thereon.

公开(公告)号：US20240304703A1

公开(公告)日：2024-09-12

申请号：US18579330

申请日：2022-07-14

Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA

Inventor： Ajey Poovannummoottil JACOB ,  Rehan Rashid KAPADIA

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/737 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/0254 ,  H01L21/02543 ,  H01L29/2003 ,  H01L29/66318 ,  H01L29/737 ,  H01L29/7786

Abstract: A method for fabricating low defective non-planar bipolar heterostructure transistors includes a steps of providing a substrate that is coated with a first dielectric layer when the substrate is not composed of a dielectric material. A layer of a first semiconductor material is formed by template liquid phase (TLP) crystal growth wherein a second dielectric layer is disposed over the first semiconductor material. A trench is patterned into the second dielectric layer. An intermediate heterostructure is formed by epitaxially growing second semiconductor material in the trench to form a fin structure therein. Various power transistor structures can be formed from the intermediate heterostructure.