公开(公告)号：US20240128179A1

公开(公告)日：2024-04-18

申请号：US18053748

申请日：2022-11-08

Applicant: Unimicron Technology Corp.

Inventor： Jyun-Hong CHEN ,  Chi-Hai KUO ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/373 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3737 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1011 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3511

Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.