公开(公告)号：US20240357748A1

公开(公告)日：2024-10-24

申请号：US18317756

申请日：2023-05-15

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Jeng-Ting LI ,  Chi-Hai KUO ,  Cheng-Ta KO ,  Pu-Ju LIN

IPC: H05K3/00 ,  H05K1/03

CPC classification number: H05K3/002 ,  H05K1/0306 ,  H05K2203/107

Abstract: A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.

公开(公告)号：US20200176369A1

公开(公告)日：2020-06-04

申请号：US16785630

申请日：2020-02-09

Applicant: Unimicron Technology Corp.

Inventor： Chun-Min WANG ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.

公开(公告)号：US20240413067A1

公开(公告)日：2024-12-12

申请号：US18360826

申请日：2023-07-28

Applicant: Unimicron Technology Corp.

Inventor： Chia-Yu PENG ,  Kai-Ming YANG ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31

Abstract: An electronic package module including a circuit substrate, an electronic component disposed on the circuit substrate and a molding compound is provided. The molding compound encapsulates the circuit substrate and the electronic component. The circuit substrate includes a first circuit layer and a first insulation layer covering on the first circuit layer. The first insulation layer has a boundary surface where a second circuit layer is disposed. A second insulation layer covers a part of the second circuit layer while the insulation layer bares a region surrounding the perimeter of the boundary surface. The molding compound directly contacts the region and the second insulation layer.

公开(公告)号：US20220071010A1

公开(公告)日：2022-03-03

申请号：US17448893

申请日：2021-09-26

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Cheng-Ta KO ,  Pu-Ju LIN ,  Chi-Hai KUO ,  Shao-Chien LEE ,  Ming-Ru CHEN ,  Cheng-Chung LO

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

公开(公告)号：US20220068742A1

公开(公告)日：2022-03-03

申请号：US17453489

申请日：2021-11-04

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Hui WU ,  Jeng-Ting LI ,  Ping-Tsung LIN ,  Kai-Ming YANG ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A chip package includes a redistribution layer, a chip, and an encapsulation member. The redistribution layer includes an insulation part, a plurality of first pads and a plurality of second pads, where the insulation part has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The first pads and the second pads are located at the first surface and the second surface respectively. The chip is disposed on the first surface and electrically connected to the first pads. The encapsulation member wraps the chip and the redistribution layer, and covers the first surface and the side surface, where the encapsulation member exposes the second pads, and the encapsulation member is not flush with the first surface and the side surface.

公开(公告)号：US20240128179A1

公开(公告)日：2024-04-18

申请号：US18053748

申请日：2022-11-08

Applicant: Unimicron Technology Corp.

Inventor： Jyun-Hong CHEN ,  Chi-Hai KUO ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/373 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3737 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1011 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3511

Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

公开(公告)号：US20230402391A1

公开(公告)日：2023-12-14

申请号：US17814527

申请日：2022-07-24

Applicant: Unimicron Technology Corp.

Inventor： Ying-Chu CHEN ,  Jeng-Ting LI ,  Chi-Hai KUO ,  Cheng-Ta KO ,  Pu-Ju LIN

IPC: H01L23/538 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5385 ,  H01L23/5383 ,  H01L23/293 ,  H01L21/4857 ,  H01L21/56

Abstract: A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.

公开(公告)号：US20230231087A1

公开(公告)日：2023-07-20

申请号：US17653659

申请日：2022-03-07

Applicant: Unimicron Technology Corp.

Inventor： Hao-Wei TSENG ,  Chi-Hai KUO ,  Jeng-Ting LI ,  Ying-Chu CHEN ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L33/54 ,  H01L25/075 ,  H01L23/00

CPC classification number: H01L33/54 ,  H01L25/0753 ,  H01L24/83 ,  H01L2933/005 ,  H01L24/29 ,  H01L2224/29194 ,  H01L2224/83099 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/8389 ,  H01L2224/83856 ,  H01L24/32 ,  H01L2224/32227 ,  H01L2924/12041

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

公开(公告)号：US20190373713A1

公开(公告)日：2019-12-05

申请号：US16543609

申请日：2019-08-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Kai-Ming YANG ,  Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN

IPC: H05K1/02 ,  H05K1/11

Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.

公开(公告)号：US20240306298A1

公开(公告)日：2024-09-12

申请号：US18668275

申请日：2024-05-20

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Cheng-Ta KO ,  Pu-Ju LIN ,  Chi-Hai KUO ,  Shao-Chien LEE ,  Ming-Ru CHEN ,  Cheng-Chung LO

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0306 ,  H05K3/0067 ,  H05K3/0094

Abstract: A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.