公开(公告)号：US20200258940A1

公开(公告)日：2020-08-13

申请号：US16735394

申请日：2020-01-06

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  David Alan Eggleston ,  Louis C. Parrillo

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.