公开(公告)号：US20230297748A1

公开(公告)日：2023-09-21

申请号：US17695093

申请日：2022-03-15

Applicant: University of Utah Research Foundation

Inventor： Ganesh Gore ,  Xifan Tang ,  Pierre-Emmanuel Gaillardon

IPC: G06F30/347

CPC classification number: G06F30/347 ,  G06F2119/12

Abstract: Technology is disclosed related to methods and devices for reducing the top-level placement and routing runtime of a field-programmable gate arrays (FPGA). The method can comprise: generating a global signal netlist comprising feedthrough connections through non-adjacent FPGA modules; selecting a predefined signal connection pattern for the global signal netlist; generating pre-routed feedthrough connections based on the predefined signal connection pattern and the global signal netlist; and generating a pre-routed global signal netlist from the pre-routed feedthrough connections. The FPGA can comprise an FPGA module configured to send a pre-routed global signal to a non-adjacent FPGA module through a pre-routed feedthrough connection identified using a predefined signal connection pattern.

公开(公告)号：US20180262197A1

公开(公告)日：2018-09-13

申请号：US15916566

申请日：2018-03-09

Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION ,  Ecole Polytechnique Federale de Lausanne

Inventor： Pierre-Emanuel Gaillardon ,  Xifan Tang ,  Gain Kim ,  Giovanni De Micheli ,  Edouard Giacomin

IPC: H03K19/173 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  H03K19/177 ,  G06F17/50

CPC classification number: H03K19/1737 ,  G06F17/5054 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1253 ,  H03K19/1776

Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.

公开(公告)号：US10348306B2

公开(公告)日：2019-07-09

申请号：US15916566

申请日：2018-03-09

Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION ,  École Polytechnique Fédérale de Lausanne

Inventor： Pierre-Emanuel Gaillardon ,  Xifan Tang ,  Gain Kim ,  Giovanni De Micheli ,  Edouard Giacomin

IPC: G11C13/00 ,  H03K19/173 ,  H01L45/00 ,  H01L27/24 ,  G06F17/50 ,  H03K19/177

Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.