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公开(公告)号:US20220274133A1
公开(公告)日:2022-09-01
申请号:US17630059
申请日:2020-07-16
Applicant: VERMON SA
Inventor: Nicolas SENEGOND , Dominique GROSS , Cyril MEYNIER
IPC: B06B1/02
Abstract: The present disclosure relates to a method of manufacturing a CMUT transducer, comprising the steps of: a) forming a first dielectric layer on a first substrate; b) forming a second dielectric layer on a second substrate; c) forming a cavity in the first or second dielectric layer; d) assembling the first and second substrates by direct bonding of the surface of the second dielectric layer opposite to the second substrate to the surface of the first dielectric layer 103) opposite to the first substrate; e) removing the second substrate to only keep above the cavity a suspended membrane formed by the second dielectric layer; and f) forming an upper electrode on the surface of the membrane opposite to the first substrate.
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公开(公告)号:US20220340410A1
公开(公告)日:2022-10-27
申请号:US17637125
申请日:2020-06-16
Applicant: VERMON SA
Inventor: Cyril MEYNIER , Dominique GROSS , Nicolas SENEGOND
Abstract: The present disclosure relates to a CUT transducer (200) comprising: —a conductive or semiconductor substrate (201) coated with a stack of one or a plurality of dielectric layers (203, 213); —a cavity (205, 215) formed in said stack; —a conductive or semiconductor membrane (221) suspended above the cavity; —at the bottom of the cavity, a conductive region (209) in contact with the upper surface of the substrate, said conductive region being interrupted on a portion of the upper surface of the substrate; and—in the cavity, a stop structure (207) made of a dielectric material localized on or above the area of interruption of the conductive region (209).
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公开(公告)号:US20230412989A1
公开(公告)日:2023-12-21
申请号:US18320000
申请日:2023-05-18
Applicant: VERMON SA
Inventor: Youngil KIM , Cyril MEYNIER , Dominique GROSS , Jacques HELLER , Nicolas SENEGOND
CPC classification number: H04R19/005 , H04R17/10 , H04R31/006
Abstract: A method of manufacturing a CMUT transducer includes: a) forming a first silicon oxide layer on a face of a first silicon layer defining a first electrode of the transducer; b) forming a second silicon oxide layer on a face of a second silicon layer; c) subsequent to step a), forming, at the side of said face of the first silicon layer, by locally oxidizing the silicon of the first silicon layer, silicon oxide walls; and d) subsequent to steps b) and c), transferring and attaching the set comprising the second silicon layer and the second silicon oxide layer on the set comprising the first silicon layer, the first silicon oxide layer, and the silicon oxide walls.
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公开(公告)号:US20220280971A1
公开(公告)日:2022-09-08
申请号:US17636198
申请日:2020-08-14
Applicant: VERMON SA
Inventor: Nicolas SENEGOND , Dominique GROSS , Cyril MEYNIER
IPC: B06B1/02
Abstract: The present disclosure relates to a method of simultaneous manufacturing, from a same substrate (101), at least one first CMUT transducer (I) having a first resonance frequency and at least one second CMUT transducer (II) having a second resonance frequency different from the first frequency, the method comprising the steps of: a) for each transducer (I, II), forming a cavity (103) on the upper surface side of the substrate, and forming a flexible membrane (105) suspended above the cavity (103); b) forming a first layer (109) extending over a portion only of the upper surface of the membrane (105) of the first transducer (I) and which does not extend over the membrane (105) of the second transducer (II); and c) forming a second layer (111) extending over the entire upper surface of the membrane (105) of the first transducer and over the entire upper surface of the membrane of the second transducer.
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公开(公告)号:US20220274134A1
公开(公告)日:2022-09-01
申请号:US17637712
申请日:2020-08-25
Applicant: VERMON SA
Inventor: Dominique GROSS , Cyril MEYNIER , Nicolas SENEGOND
IPC: B06B1/02
Abstract: The present disclosure relates to a CMUT transducer (200) comprising: a substrate (101) coated with a dielectric layer (103); a cavity (105) formed in the dielectric layer (103); a conductive or semiconductor membrane (107) suspended above the cavity (105); and a dielectric coating (104) arranged on an upper surface of the substrate (101) at the bottom of the cavity or on a lower surface of the membrane at the top of the cavity and extending, in top view, on the most part of the surface of the cavity (105), wherein the dielectric coating (104) is structured opposite the cavity (105).
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