公开(公告)号：US20210159119A1

公开(公告)日：2021-05-27

申请号：US17061185

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu CHUANG

IPC: H01L21/768 ,  H01L27/11521

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a lining layer on a substrate and a plurality of gate structures; forming a first spacer layer on the lining layer; forming a stop layer on the first spacer layer; forming a first sacrificial layer on the stop layer and between the gate structures; removing a portion of the first sacrificial layer so that the top surface of the first sacrificial layer is located between the upper portions of the gate structures; forming a second spacer layer on the first sacrificial layer and the gate structures; and removing a portion of the second spacer layer so that the remaining second spacer layer is located between the upper portions of the gate structures.

公开(公告)号：US20190181063A1

公开(公告)日：2019-06-13

申请号：US16155496

申请日：2018-10-09

Applicant: Winbond Electronics Corp.

Inventor： Hsiu-Han LIAO ,  Che-Fu CHUANG

IPC: H01L21/66 ,  H01L23/544 ,  H01L23/58 ,  H01L23/00

Abstract: A semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A test pad structure and a test element are disposed over the semiconductor substrate corresponding to the scribe line region. A conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the test pad structure and the test element.

公开(公告)号：US20220320127A1

公开(公告)日：2022-10-06

申请号：US17472912

申请日：2021-09-13

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu CHUANG ,  Hsiu-Han LIAO

IPC: H01L27/11541

Abstract: A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

公开(公告)号：US20210151447A1

公开(公告)日：2021-05-20

申请号：US17061442

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu CHUANG ,  Jian-Ting CHEN ,  Yu-Kai LIAO ,  Hsiu-Han LIAO

IPC: H01L27/11517 ,  H01L29/66

Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.