公开(公告)号：US20250098250A1

公开(公告)日：2025-03-20

申请号：US18780512

申请日：2024-07-23

Applicant: Winbond Electronics Corp.

Inventor： Noriaki Ikeda ,  Chun-Sheng Yang ,  Hao-Chuan Chang

IPC: H01L29/161 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor structure including a substrate, a first electrode, a first dielectric layer, and a second electrode is provided. The first electrode is located on the substrate. The first electrode is pillar-shaped. The first dielectric layer is located on the first electrode. The second electrode is located on the first dielectric layer. The second electrode includes a first silicon germanium (SiGe) layer and a second SiGe layer. The first SiGe layer is located on the first dielectric layer. The second SiGe layer is located on the first SiGe layer. A content of germanium in the second SiGe layer is greater than a content of germanium in the first SiGe layer.

公开(公告)号：US20240389305A1

公开(公告)日：2024-11-21

申请号：US18639992

申请日：2024-04-19

Applicant: Winbond Electronics Corp.

Inventor： Noriaki Ikeda ,  Chun-Sheng Yang ,  Hsing-Hao Chen

IPC: H10B12/00

Abstract: A semiconductor structure including the following components is provided. Stack structures are located on a substrate and separated from each other. Isolation layers are located on the sidewalls of the stack structures. A contact is located on the substrate between two adjacent isolation layers. A landing pad is located on the contact. The landing pad is located on one of the two adjacent isolation layers. There is an opening on one side of the landing pad. A first dielectric layer is located in the opening. A porous dielectric layer is located between the first dielectric layer and the landing pad. The top surface of the porous dielectric layer is lower than the top surface of the landing pad and the top surface of the first dielectric layer to form a recess between the landing pad and the first dielectric layer. The recess exposes the sidewall of the landing pad.

公开(公告)号：US20220359525A1

公开(公告)日：2022-11-10

申请号：US17580610

申请日：2022-01-20

Applicant: Winbond Electronics Corp.

Inventor： Chun-Sheng Yang ,  Hsing-Hao Chen

IPC: H01L27/108

Abstract: Provided is a memory device including a substrate, a plurality of bit-line structures, a plurality of bit-line contacts, and a plurality of protective structures. The substrate has a plurality of active areas. The plurality of bit-line structures are disposed on the substrate in parallel along a X direction. The plurality of bit-line contacts are respectively disposed at overlaps of the plurality of bit-line structures and the plurality of active areas, and electrically connect the plurality of bit-line structures and the plurality of active areas. The plurality of protective structures are disposed at least on a first sidewall and a second sidewall of the plurality of bit-line contacts. A method of forming a memory device is also provided.