公开(公告)号：US11557595B2

公开(公告)日：2023-01-17

申请号：US16925603

申请日：2020-07-10

Applicant: Winbond Electronics Corp.

Inventor： Shu-Ming Lee ,  Tzu-Ming Ou Yang ,  Meng-Chang Chan

IPC: H01L21/768 ,  H01L27/11519 ,  H01L27/11526

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

公开(公告)号：US10756099B2

公开(公告)日：2020-08-25

申请号：US16382743

申请日：2019-04-12

Applicant: Winbond Electronics Corp.

Inventor： Shu-Ming Lee ,  Tzu-Ming Ou Yang ,  Meng-Chang Chan

IPC: H01L21/768 ,  H01L27/11519 ,  H01L27/11526

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

公开(公告)号：US10483235B2

公开(公告)日：2019-11-19

申请号：US15057973

申请日：2016-03-01

Applicant: Winbond Electronics Corp.

Inventor： Yu-Cheng Chiao ,  Tung-Yi Chan ,  Chen-Hsi Lin ,  Chia Hua Ho ,  Meng-Chang Chan ,  Hsin-Hung Chou

IPC: H01L25/065

Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

公开(公告)号：US20200343255A1

公开(公告)日：2020-10-29

申请号：US16925603

申请日：2020-07-10

Applicant: Winbond Electronics Corp.

Inventor： Shu-Ming Lee ,  Tzu-Ming Ou Yang ,  Meng-Chang Chan

IPC: H01L27/11519 ,  H01L27/11526

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

公开(公告)号：US09881901B2

公开(公告)日：2018-01-30

申请号：US15015919

申请日：2016-02-04

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Yu-Cheng Chiao ,  Tung-Yi Chan ,  Chen-Hsi Lin ,  Chia Hua Ho ,  Meng-Chang Chan ,  Hsin-Hung Chou

IPC: H01L21/44 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2225/06506 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.