公开(公告)号：US20240332418A1

公开(公告)日：2024-10-03

申请号：US18448541

申请日：2023-08-11

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ting CHEN ,  Kai JEN

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66666

Abstract: A semiconductor device includes: a substrate; a source region disposed on the substrate; a drain region disposed on the source region; and a floating main body region disposed between the source region and the drain region. The floating main body region vertically separates the source region from the drain region. The semiconductor device further includes: a gate region laterally wrapped around the floating main body region; and a gate dielectric located between the floating main body region and the gate region, and insulated the floating main body region from the gate region. A material of the gate dielectric has a negative capacitance feature.

公开(公告)号：US20240057316A1

公开(公告)日：2024-02-15

申请号：US18447851

申请日：2023-08-10

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ting CHEN ,  Wei-Che CHANG

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/053

Abstract: A buried gate structure and a method for forming the same are provided. The structure includes first and second gate dielectric layers respectively formed on the surface of the lower portion and the surface of the upper portion of a gate trench of the semiconductor substrate. The structure includes a first gate electrode formed on the first gate dielectric layer. The structure includes an insulating cap layer formed on the first gate electrode to fill the remaining space of the gate trench. The first gate dielectric layer includes a negative capacitance dielectric material. The second gate dielectric layer includes a different dielectric material than the negative capacitance dielectric material. The interface between the first gate dielectric layer and the second gate dielectric layer is lower than the bottom surfaces of the source region and the drain region of the semiconductor substrate.

公开(公告)号：US20190213468A1

公开(公告)日：2019-07-11

申请号：US15868392

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Frederick CHEN ,  Ping-Kun WANG ,  Shao-Ching LIAO ,  Chih-Cheng FU ,  Ming-Che LIN ,  Yu-Ting CHEN ,  Seow-Fong (Dennis) LIM

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/0635 ,  G06N3/08 ,  G11C13/0002

Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.