公开(公告)号：US20210249436A1

公开(公告)日：2021-08-12

申请号：US17112496

申请日：2020-12-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei DING ,  Jing GAO ,  Chuan YANG ,  Lan Fang YU ,  Ping YAN ,  Sen ZHANG ,  Bo XU

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

公开(公告)号：US20190148401A1

公开(公告)日：2019-05-16

申请号：US16220000

申请日：2018-12-14

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DING Lei ,  Jing GAO ,  Chuan YANG ,  Lan Fang YU ,  Ping YAN ,  Sen ZHANG ,  Bo XU

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

公开(公告)号：US20230284445A1

公开(公告)日：2023-09-07

申请号：US18316109

申请日：2023-05-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20200335514A1

公开(公告)日：2020-10-22

申请号：US16918683

申请日：2020-07-01

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H01L27/11578 ,  H01L27/11575 ,  H01L21/762 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20190081059A1

公开(公告)日：2019-03-14

申请号：US16046818

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H01L27/11578 ,  H01L27/11565 ,  H01L27/1157

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20210167076A1

公开(公告)日：2021-06-03

申请号：US16797030

申请日：2020-02-21

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wenxiang XU ,  Haohao YANG ,  Pan HUANG ,  Ping YAN ,  Zongliang HUO ,  Wenbin ZHOU ,  Wei XU

IPC: H01L27/11539 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line silts in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.