公开(公告)号：US20240215458A1

公开(公告)日：2024-06-27

申请号：US18089838

申请日：2022-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuxuan FANG ,  Shan LI ,  Dongxue ZHAO ,  Lei LIU ,  Zhiliang XIA

IPC: H10N50/10 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/10 ,  H01L23/5283 ,  H10B61/20 ,  H10N50/01

Abstract: A memory device includes a semiconductor layer and a stack structure over the semiconductor layer. The stack structure includes a cell array region and a staircase structure region. The cell array region includes multiple vertical levels of stacked transistor-magnetic tunnel junction (TMTJ) elements and a plurality of channel structures vertically extending through the stack structure. At least one channel structure includes a vertical core, a vertical magnetic reference layer, and a vertical tunnel barrier layer, which are shared by a set of magnetic tunnel junction (MTJ) elements associated with the at least one channel structure. The set of MTJ elements are located at different vertical levels of the stack structure.

公开(公告)号：US20240215237A1

公开(公告)日：2024-06-27

申请号：US18090049

申请日：2022-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yi YANG ,  Tingting GAO ,  Xiaoxin LIU ,  Wei YUAN ,  Xiaolong DU ,  Changzhi SUN ,  Zhihao SONG ,  Shan LI ,  Zhiliang XIA ,  Zongliang HUO

IPC: H10B43/27 ,  H10B41/27 ,  H10B80/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B80/00

Abstract: A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening that exposes the sacrificial layer, removing the sacrificial layer to create a cavity and expose a part of the channel hole structure, forming a semiconductor layer to fill the cavity, filling the opening with a filling structure, and forming a second dielectric stack over the filling structure. The opening is made for a gate line slit (GLS) structure.