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    NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS
    1.
    发明申请
    NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS 有权

    公开(公告)号：US20250111880A1

    公开(公告)日：2025-04-03

    申请号：US18977750

    申请日：2024-12-11

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Tao YANG ,  Dongxue ZHAO ,  Lei LIU ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

    IPC: G11C16/16 ,  G11C16/04

    Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

    THREE-DIMENSIONAL NAND MEMORY AND FABRICATION METHOD THEREOF
    3.
    发明申请
    THREE-DIMENSIONAL NAND MEMORY AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20220359561A1

    公开(公告)日：2022-11-10

    申请号：US17566352

    申请日：2021-12-30

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Yuancheng YANG ,  Lei LIU ,  Wenxi ZHOU

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/04

    Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack that includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate; forming a channel structure penetrating through the alternating dielectric stack in a first direction perpendicular to the substrate. The channel structure includes a charge trapping layer extending in the first direction. The method also includes removing at least one second dielectric layer at a top portion of the alternating dielectric stack to form a top select gate (TSG) cut tunnel and to expose a portion of the charge trapping layer in a second direction parallel to the substrate. The method further includes removing the exposed portion of the charge trapping layer inside the TSG cut tunnel; and disposing a TSG conductive layer inside the TSG cut tunnel.

    MEMORY DEVICE AND METHOD OF FORMING THE SAME
    7.
    发明公开
    MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240215458A1

    公开(公告)日：2024-06-27

    申请号：US18089838

    申请日：2022-12-28

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Yuxuan FANG ,  Shan LI ,  Dongxue ZHAO ,  Lei LIU ,  Zhiliang XIA

    IPC: H10N50/10 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01

    CPC classification number: H10N50/10 ,  H01L23/5283 ,  H10B61/20 ,  H10N50/01

    Abstract: A memory device includes a semiconductor layer and a stack structure over the semiconductor layer. The stack structure includes a cell array region and a staircase structure region. The cell array region includes multiple vertical levels of stacked transistor-magnetic tunnel junction (TMTJ) elements and a plurality of channel structures vertically extending through the stack structure. At least one channel structure includes a vertical core, a vertical magnetic reference layer, and a vertical tunnel barrier layer, which are shared by a set of magnetic tunnel junction (MTJ) elements associated with the at least one channel structure. The set of MTJ elements are located at different vertical levels of the stack structure.

    METHOD AND APPARATUS FOR DATA ERASE IN MEMORY DEVICES
    8.
    发明申请
    METHOD AND APPARATUS FOR DATA ERASE IN MEMORY DEVICES 有权

    公开(公告)号：US20220351781A1

    公开(公告)日：2022-11-03

    申请号：US17866999

    申请日：2022-07-18

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

    Abstract: Aspects of the disclosure provide an erase method for a memory device. In the method, during a time period, a first positive voltage is applied to a body portion of a memory cell string of the memory device. The memory cell string includes memory cell transistors and select transistors connected in series. A second positive voltage is applied to a bit line signal of the memory cell string. A third positive voltage is applied to a first top select gate signal to turn on a first top select transistor of the select transistors so that the memory cell transistors are coupled to the bit line signal through the first top select transistor. A ground level voltage or a fourth positive voltage is applied to a word line signal of the memory cell transistors. Both the third and fourth positive voltages are less than the second positive voltage.

    NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS
    9.
    发明公开
    NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS 审中-公开

    公开(公告)号：US20240105266A1

    公开(公告)日：2024-03-28

    申请号：US17950931

    申请日：2022-09-22

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Tao YANG ,  Dongxue ZHAO ,  Lei LIU ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

    IPC: G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/0483

    Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

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