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    METHOD FOR FABRICATING LIQUID CRYSTAL DISPLAY
    1.
    发明申请
    METHOD FOR FABRICATING LIQUID CRYSTAL DISPLAY 有权
    用于制造液晶显示器的方法

    公开(公告)号：US20140363914A1

    公开(公告)日：2014-12-11

    申请号：US14297601

    申请日：2014-06-05

    Applicant: Ye Xin Technology Consulting Co., Ltd.

    Inventor： YI-CHUN KAO

    IPC: H01L27/12 ,  H01L21/28

    CPC classification number: H01L27/1259 ,  G02F1/13452 ,  G02F1/136227 ,  H01L21/28247 ,  H01L27/1244 ,  H01L27/1288

    Abstract: Method for manufacturing a thin film transistor liquid crystal display is provided. A substrate is provided. A gate electrode, a source electrode, a drain electrode, and a passivation film are formed on the substrate in sequence. The passivation film has a contact hole to expose a part of the drain electrode. A conductive layer is formed by coating nano metal material on the passivation film and in the contract hole from which the drain electrode is exposed. A pixel electrode is formed by patterning the conductive layer.

    Abstract translation: 提供了制造薄膜晶体管液晶显示器的方法。 提供基板。 依次在基板上形成栅电极，源电极，漏电极和钝化膜。 钝化膜具有露出一部分漏电极的接触孔。 通过将钝化膜上的纳米金属材料和漏电极露出的收缩孔中涂覆导电层。 通过图案化导电层形成像素电极。

    SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME
    2.
    发明申请
    SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME 审中-公开
    自对准金属氧化物薄膜晶体管及其制造方法

    公开(公告)号：US20160268444A1

    公开(公告)日：2016-09-15

    申请号：US15162561

    申请日：2016-05-23

    Applicant: Ye Xin Technology Consulting Co., Ltd.

    Inventor： KUO-LUNG FANG ,  YI-CHUN KAO ,  PO-LI SHIH ,  CHIH-LUNG LEE ,  HSIN-HUA LIN

    IPC: H01L29/786 ,  H01L29/66 ,  H01L21/425

    CPC classification number: H01L29/78696 ,  H01L21/425 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.

    Abstract translation: 薄膜晶体管包括基板，形成在基板上的栅电极，覆盖栅电极的电绝缘层，形成在电绝缘层上的由半导体材料制成的沟道层，形成在第一侧面上的源电极 的电绝缘层，以及形成在电绝缘层的相对的第二横向侧上的漏电极。 源电极具有覆盖沟道层的第一外端并与之电连接的内端。 漏电极具有覆盖通道层的相对的第二外端并与之电连接的内端。 与源电极和漏电极中的一个相邻并且未被其覆盖的沟道层的区域的导电率低于沟道层的其它区域的导电率。

    DISPLAY ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    DISPLAY ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    显示阵列基板及其制造方法

    公开(公告)号：US20150279976A1

    公开(公告)日：2015-10-01

    申请号：US14556731

    申请日：2014-12-01

    Applicant: Ye Xin Technology Consulting Co., Ltd.

    Inventor： PO-LI SHIH ,  YI-CHUN KAO

    IPC: H01L29/66 ,  H01L29/786

    CPC classification number: H01L27/1214 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

    Abstract: A manufacturing method of display array substrate is provided. The method includes depositing a first metal layer on a substrate and defining a peripheral area and a display area, coating a photo-resist layer on the first metal layer located in the peripheral area, anodizing the first metal layer to a first metal oxide layer with the photo-resist layer as a mask, patterning the first metal oxide layer located in the display area to a gate insulator, removing the photo-resist layer to expose the first metal layer in the peripheral area, forming a channel layer on the gate insulator, and depositing a second metal layer and patterning the second metal layer located in the display area to form a source electrode and a drain electrode.

    Abstract translation: 提供了一种显示阵列基板的制造方法。 该方法包括在衬底上沉积第一金属层并限定外围区域和显示区域，在位于周边区域的第一金属层上涂覆光致抗蚀剂层，将第一金属层阳极氧化为第一金属氧化物层， 作为掩模的光致抗蚀剂层，将位于显示区域中的第一金属氧化物层图案化成栅极绝缘体，去除光致抗蚀剂层以露出周边区域中的第一金属层，在栅极绝缘体上形成沟道层 并且沉积第二金属层并且图案化位于显示区域中的第二金属层以形成源电极和漏电极。

    SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME
    7.
    发明申请
    SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME 有权
    自对准金属氧化物薄膜晶体管及其制造方法

    公开(公告)号：US20160190326A1

    公开(公告)日：2016-06-30

    申请号：US14591189

    申请日：2015-01-07

    Applicant: Ye Xin Technology Consulting Co., Ltd.

    Inventor： KUO-LUNG FANG ,  YI-CHUN KAO ,  PO-LI SHIH ,  CHIH-LUNG LEE ,  HSIN-HUA LIN

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/78696 ,  H01L21/425 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

    Abstract: A method for forming a TFT includes providing a substrate, a gate electrode on the substrate, an electrically insulating layer on the substrate to totally cover the gate electrode, a channel layer on the electrically insulating layer, a first photoresist pattern on the channel layer, a metal layer on the electrically insulating layer, the channel layer and the first photoresist layer, and a second photoresist pattern on the metal layer. A middle portion of the metal layer is then removed to form a source electrode and a drain electrode and to expose the first photoresist pattern and a portion of the channel layer between the first and second photoresist patterns. The exposed portion of the channel layer is then processed to have its electrical conductivity be lowered to thereby reduce a hot-carrier effect of the channel layer.

    Abstract translation: 一种用于形成TFT的方法，包括：在基板上设置基板，栅电极，在基板上形成电绝缘层，以完全覆盖栅电极，电绝缘层上的沟道层，沟道层上的第一光刻胶图案， 电绝缘层上的金属层，沟道层和第一光致抗蚀剂层，以及金属层上的第二光致抗蚀剂图案。 然后去除金属层的中间部分以形成源电极和漏电极，并且在第一和第二光致抗蚀剂图案之间露出第一光致抗蚀剂图案和沟道层的一部分。 然后处理通道层的暴露部分以使其导电性降低，从而降低沟道层的热载流子效应。

    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL USING SAME
    8.
    发明申请
    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL USING SAME 有权
    薄膜晶体管阵列基板和使用相同的液晶显示面板

    公开(公告)号：US20160155856A1

    公开(公告)日：2016-06-02

    申请号：US14697154

    申请日：2015-04-27

    Applicant: Ye Xin Technology Consulting Co., Ltd.

    Inventor： HSIN-HUA LIN ,  YI-CHUN KAO

    IPC: H01L29/786 ,  H01L27/12 ,  G02F1/1335 ,  G02F1/1368 ,  G02F1/1362

    CPC classification number: H01L29/78606 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1248

    Abstract: A thin film transistor (TFT) array substrate of a liquid crystal display (LCD) panel includes a first substrate, a gate located on the first substrate, a gate insulation layer located on the first substrate and covers the gate and the first substrate, a source layer located on the gate insulation layer to correspond to the gate, an etching stopping layer located on the source layer, and a source and a drain located on the etching stopping layer. The etching stopping layer is made of color photoresist.

    Abstract translation: 液晶显示器（LCD）面板的薄膜晶体管（TFT）阵列基板包括第一基板，位于第一基板上的栅极，位于第一基板上并覆盖栅极和第一基板的栅极绝缘层， 源极层，位于栅极绝缘层上以对应于栅极，位于源极层上的蚀刻停止层以及位于蚀刻停止层上的源极和漏极。 蚀刻停止层由彩色光致抗蚀剂制成。

    THIN FILM TRANSISTOR AND DISPLAY ARRAY SUBSTRATE USING SAME
    10.
    发明申请
    THIN FILM TRANSISTOR AND DISPLAY ARRAY SUBSTRATE USING SAME 有权
    薄膜晶体管和显示阵列基板使用相同

    公开(公告)号：US20150053974A1

    公开(公告)日：2015-02-26

    申请号：US14467444

    申请日：2014-08-25

    Applicant: Ye Xin Technology Consulting Co., Ltd.

    Inventor： I-WEI WU ,  I-MIN LU ,  WEI-CHIH CHANG ,  HUI-CHU LIN ,  YI-CHUN KAO ,  KUO-LUNG FANG

    IPC: H01L27/12 ,  H01L21/308 ,  H01L29/786

    CPC classification number: H01L29/7869 ,  H01L21/31058 ,  H01L21/31144 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78606

    Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

    Abstract translation: 薄膜晶体管包括栅电极，栅极绝缘层，沟道层，蚀刻停止层，两个接触孔，源极和漏极。 栅极绝缘层覆盖栅电极。 沟道层布置在对应于栅电极的栅极绝缘层上。 蚀刻停止层覆盖沟道层并且包括有机阻挡层和硬掩模层，硬掩模层位于与沟道层相对的有机阻挡层的表面上，以提高有机阻挡层的硬度。 两个接触孔穿过蚀刻停止层。 源极通过一个接触孔连接到通道，漏极通过另一个接触孔连接到通道。

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