公开(公告)号：US20110176346A1

公开(公告)日：2011-07-21

申请号：US13007086

申请日：2011-01-14

Applicant: Yukio KATAMURA

Inventor： Yukio KATAMURA

IPC: G11C5/02

CPC classification number: H01L25/0652 ,  H01L25/165 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/18161 ,  H01L2924/19106 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2203/1316 ,  H01L2224/05599

Abstract: According to one embodiment, semiconductor memory device including: a circuit substrate in which a circuit pattern is formed; a plurality of semiconductor memories mounted via a solder on both surfaces of the circuit substrate; a connector disposed at one end part of the circuit substrate for connection with a host device; and a resin mold part that seals the both surfaces of the circuit substrate. The resin mold part does not seal a region in which the connector is disposed and collectively seals regions in which the plurality of semiconductor memories are disposed.

Abstract translation: 根据一个实施例，半导体存储器件包括：形成电路图案的电路基板; 多个半导体存储器，其通过焊料安装在电路基板的两个表面上; 连接器，设置在电路基板的一个端部，用于与主机设备连接; 以及密封电路基板的两面的树脂模具部。 树脂模具部分不密封其中设置连接器的区域，并且集中地密封其中设置有多个半导体存储器的区域。

公开(公告)号：US20120149151A1

公开(公告)日：2012-06-14

申请号：US13226152

申请日：2011-09-06

Applicant: Yasuo TANE ,  Yukio KATAMURA ,  Atsushi YOSHIMURA ,  Fumihiro IWAMI

Inventor： Yasuo TANE ,  Yukio KATAMURA ,  Atsushi YOSHIMURA ,  Fumihiro IWAMI

IPC: H01L21/50

CPC classification number: H01L25/50 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3121 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/93 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/27312 ,  H01L2224/27848 ,  H01L2224/27901 ,  H01L2224/29016 ,  H01L2224/29017 ,  H01L2224/29018 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/33183 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05599

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.

Abstract translation: 根据一个实施例，制造半导体器件的方法，在半导体晶片的芯片区域的第一表面上形成接合层。 半导体芯片沿切割区域分割。 半导体芯片经由接合层逐级层叠。 在半导体芯片的接合层的形成中，在层叠状态的第一面的第一区域的第一区域与其他半导体芯片不接触的情况下，形成接合层的突出部比形成 提供与另一半导体芯片接触的第二区域中的层。

公开(公告)号：US20120052627A1

公开(公告)日：2012-03-01

申请号：US13052144

申请日：2011-03-21

Applicant: Yukio KATAMURA ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

Inventor： Yukio KATAMURA ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC: H01L21/50

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/27312 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.

Abstract translation: 根据一个实施例，公开了一种用于制造半导体器件的方法，该半导体器件包括具有形成在第一主表面上的电极焊盘和设置在第二主表面上的接合层的半导体芯片，以及具有安装在该衬底上的半导体芯片的衬底。 制造方法可以包括在基板的前表面上将接合成形材料的半导体芯片的第二主表面的外边缘接触的部分。 该方法可以包括通过接合层将半导体芯片的第二主表面接合到衬底。

公开(公告)号：US20110263131A1

公开(公告)日：2011-10-27

申请号：US13008443

申请日：2011-01-18

Applicant: Yukio KATAMURA ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

Inventor： Yukio KATAMURA ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC: H01L21/302 ,  B05B15/00 ,  B05B1/02

CPC classification number: H01L21/6715 ,  H01L21/67109 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/27901 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/743 ,  H01L2224/83191 ,  H01L2224/94 ,  Y10T156/10 ,  H01L2224/27 ,  H01L2924/00

Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.

Abstract translation: 在一个实施例中，公开了一种用于制造半导体器件的方法。 该方法可以包括在将包含树脂和溶剂的粘合材料附着到与包括晶片的电路图案的第一表面相对的第二表面时，加热粘合材料以蒸发溶剂并降低溶剂的蒸气压 气氛面临着接合材料并加热附着的接合材料以形成接合层。

公开(公告)号：US20110263097A1

公开(公告)日：2011-10-27

申请号：US13053959

申请日：2011-03-22

Applicant: Atsushi YOSHIMURA ,  Yasuo TANE ,  Yukio KATAMURA ,  Fumihiro IWAMI

Inventor： Atsushi YOSHIMURA ,  Yasuo TANE ,  Yukio KATAMURA ,  Fumihiro IWAMI

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2221/68386

Abstract: According to one embodiment, a method for manufacturing semiconductor device can include forming a groove with a depth shallower than a thickness of a wafer. The method can include attaching a surface protection tape via a first bonding layer provided in the surface protection tape. The method can include grinding a surface of the wafer to divide the wafer into a plurality of semiconductor elements. The method can include forming an element bonding layer by attaching a bonding agent and turning the attached bonding agent into a B-stage state. The method can include attaching a dicing tape via a second bonding layer provided in the dicing tape. The method can include irradiating the first bonding layer with a first active energy ray. The method can include removing the surface protection tape. The method can include irradiating the second bonding layer with a second active energy ray.

Abstract translation: 根据一个实施例，半导体器件的制造方法可以包括形成深度比晶片厚度更深的凹槽。 该方法可以包括通过设置在表面保护带中的第一粘合层附接表面保护带。 该方法可以包括研磨晶片的表面以将晶片分成多个半导体元件。 该方法可以包括通过附着粘合剂形成元件结合层并将附着的粘接剂转化为B阶状态。 该方法可以包括通过设置在切割带中的第二粘合层附着切割带。 该方法可以包括用第一活性能量射线照射第一结合层。 该方法可以包括去除表面保护带。 该方法可以包括用第二活性能量射线照射第二结合层。