Invention Grant
- Patent Title: 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same
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Application No.: US17136820Application Date: 2020-12-29
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Publication No.: US11631671B2Publication Date: 2023-04-18
- Inventor: H. Jim Fulford , Anton J. Devilliers , Mark I. Gardner , Daniel Chanemougame , Jeffrey Smith , Lars Liebmann , Subhadeep Kal
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/786 ; H01L29/16 ; H01L21/8238

Abstract:
A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.
Public/Granted literature
- US20210202481A1 3D COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE AND METHOD OF FORMING THE SAME Public/Granted day:2021-07-01
Information query
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