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    METHOD OF FABRICATING A SUPPORT STRUCTURE
    2.
    发明申请
    METHOD OF FABRICATING A SUPPORT STRUCTURE 审中-公开
    支持结构的方法

    公开(公告)号：WO03028915A9

    公开(公告)日：2004-12-29

    申请号：PCT/US0231075

    申请日：2002-10-01

    Applicant: CANDESCENT INTELLECTUAL PROP

    Inventor： FAHLEN THEODORE S ,  HOPPLE GEORGE B ,  PORTER JOHN D ,  BARTON ROGER W ,  MACKEY BOB L

    IPC: B23P25/00 ,  B32B17/10 ,  C03C17/00 ,  C03C17/36 ,  H01J9/24 ,  H01J29/70 ,  B21D47/00

    CPC classification number: C03C17/36 ,  B32B17/10018 ,  C03C17/002 ,  C03C2217/40 ,  C03C2218/335 ,  H01J9/242 ,  H01J2211/36 ,  H01J2329/00 ,  H01J2329/8625 ,  Y10T29/49126 ,  Y10T29/49616 ,  Y10T29/49812 ,  Y10T29/49885 ,  Y10T29/49904 ,  Y10T29/4998

    Abstract: A method of fabricating a support structure (118). In one embodiment, the method is comprised of providing a mold (220). The mold (220) is for defining the physical dimension of the support structure. The mold (220) is disposed upon a substrate surface (210). In one embodiment, the method is further comprised of depositing a powder (230) into the mold (220). The present method is further comprised of compacting the powder (230) deposited in the mold (220). The compacting forms the support structure (118). In one embodiment, the method is further comprised of removing the mold (220) from the substrate surface (210) upon which it is disposed. The removal of the mold (220) exposes the support structure (118). The fabricated support structure (118) is then implementable during assembly of a display device (100). In one embodiment, the powder (230) deposited in the mold (220) is a metal powder (230).

    Abstract translation: 一种制造支撑结构（118）的方法。 在一个实施例中，该方法包括提供模具（220）。 模具（220）用于限定支撑结构的物理尺寸。 模具（220）设置在基板表面（210）上。 在一个实施例中，该方法还包括将粉末（230）沉积到模具（220）中。 本方法还包括压实沉积在模具（220）中的粉末（230）。 压实形成支撑结构（118）。 在一个实施例中，该方法还包括从其上设置的基板表面（210）移除模具（220）。 模具（220）的移除使支撑结构（118）暴露。 然后，在组装显示装置（100）期间可以实现制造的支撑结构（118）。 在一个实施例中，沉积在模具（220）中的粉末（230）是金属粉末（230）。

    STRUCTURE, FABRICATION, AND CORRECTIVE TEST OF ELECTRON-EMITTING DEVICE HAVING ELECTRODE CONFIGURED TO REDUCE CROSS-OVER CAPACITANCE AND/OR FACILITATE SHORT-CIRCUIT REPAIR
    3.
    发明申请
    STRUCTURE, FABRICATION, AND CORRECTIVE TEST OF ELECTRON-EMITTING DEVICE HAVING ELECTRODE CONFIGURED TO REDUCE CROSS-OVER CAPACITANCE AND/OR FACILITATE SHORT-CIRCUIT REPAIR 审中-公开
    具有配置的电极的电子发射装置的结构，制造和校正测试可以减少交叉电容和/或简化短路电路维修

    公开(公告)号：WO03050848A9

    公开(公告)日：2004-05-27

    申请号：PCT/US0238812

    申请日：2002-12-03

    Applicant: CANDESCENT INTELLECTUAL PROP ,  SONY CORP

    Inventor： RADIGAN STEVEN J ,  BONN MATTHEW A ,  KEMMOTSU HIDENORI ,  FAHLEN THEODORE S

    IPC: H01J3/02 ,  H01J1/30 ,  H01J1/304 ,  H01J1/46

    CPC classification number: H01J3/022

    Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

    Abstract translation: 电子发射器件（20,70,80或90）包含电极，控制电极（38）或发射极（32），其具有位于电极本体侧面的特定部分。 对于控制电极，指定部分是具有露出位于发射极上方的电子发射元件（50A或50B）的开口的曝光部分（38EA或38EB）。 对于发射电极，指定的部分是位于通过控制电极中的至少一个开口暴露的至少一个电子发射元件下面的发射极耦合部分。 以这种方式配置器件使控制电极对发射极之间的电容非常小，从而提高器件的开关速度。 如果电极的指定部分与另一个电极短路，则可以通过从电极的其余部分切断指定部分来消除短路缺陷。

    METHOD FOR IMPLEMENTING A 6-MASK CATHODE PROCESS
    4.
    发明申请
    METHOD FOR IMPLEMENTING A 6-MASK CATHODE PROCESS 审中-公开
    用于实施6掩蔽阴极过程的方法

    公开(公告)号：WO03030200A9

    公开(公告)日：2004-04-22

    申请号：PCT/US0230618

    申请日：2002-09-25

    Applicant: CANDESCENT INTELLECTUAL PROP ,  SONY CORP

    Inventor： LEE JUENG-GIL ,  KIKUCHI KAZUO ,  BONN MATTHEW A

    IPC: H01J9/02 ,  H01J1/304 ,  H01J5/46 ,  H01J9/24

    CPC classification number: H01J9/025

    Abstract: A method for forming an electrical connection via through the interlayer dielectric sandwiched between upper and lower electrode layers of a display panel substrate comprising a step (901) of depositing a passivation layer on a chromium layer overlying a conductive layer which is deposited on the interlayer dielectric, a step (903, 903(a)) of patterning and etching the passivation layer, and a step (904) of etching the interlayer dielectric using the passivation layer as a mask. One embodiment is characterized in that a convention step of depositing a second passivation layer and corresponding process steps is unnecessary. Such embodiment employs a gasous etchant comprised of a mixture of gases such as (a) sulfur hexafluoride, carbon tetrafluoride, trifluororomethane and oxygen or (b) octafluorocyclobutane, acrbon monoxide and argon to etch a silicon nitride passivation layer (step 903) and a wet etch to selectively etch a silicon dioxide interlayer dielectric (step 904). A further process step may comprise a dual resister layer etching step (906) to expose the lower electrode layer where necessary.

    Abstract translation: 一种用于通过夹在显示面板基板的上电极层和下电极层之间的层间电介质形成电连接的方法，包括在沉积在层间电介质上的导电层上的铬层上沉积钝化层的步骤（901） ，图案化和蚀刻钝化层的步骤（903,903（a）），以及使用钝化层作为掩模蚀刻层间电介质的步骤（904）。 一个实施例的特征在于，不需要沉积第二钝化层的常规步骤和相应的处理步骤。 这种实施方案采用气体蚀刻剂，其由诸如（a）六氟化硫，四氟化碳，三氟甲烷和氧气的混合气体组成，或（b）八氟环丁烷，一氧化碳和氩气以蚀刻氮化硅钝化层（步骤903）和湿润 蚀刻以选择性地蚀刻二氧化硅层间电介质（步骤904）。 另外的工艺步骤可以包括在需要时暴露下电极层的双电阻层蚀刻步骤（906）。

    METHOD FOR IMPLEMENTING AN EFFICIENT AND ECONOMICAL CATHODE PROCESS
    9.
    发明申请
    METHOD FOR IMPLEMENTING AN EFFICIENT AND ECONOMICAL CATHODE PROCESS 审中-公开
    实施有效和经济阴极过程的方法

    公开(公告)号：WO03030185A9

    公开(公告)日：2003-12-11

    申请号：PCT/US0230612

    申请日：2002-09-25

    Applicant: CANDESCENT INTELLECTUAL PROP ,  SONY CORP

    Inventor： LEE JUENG-GIL ,  BONN MATTHEW A ,  KEMMOTSU HIDENORI ,  KIKUCHI KAZUO

    IPC: H01J1/30 ,  H01J9/02 ,  H01B13/00

    CPC classification number: H01J9/148 ,  H01J1/30

    Abstract: The present writing reveals a method of fabricating a cathode requiring relatively few and somewhat simple steps. A novel etchant gas chemistry dispenses with needing a second passivation layer (PA2). A direct via is formed without a separate mask. Access and isolation features of a metallic gate (MG) are patterned in the same patterning operation as an associated passivation layer, dispensing with a need for separate patterning of each. Etching is effectuated with high selectivity for nitrides of silicon. The requirement for at least one passivation layer deposition, a direct via masking step, and separate patterning steps for the passivation layer and metallic gate are eliminated.

    Abstract translation: 本文件揭示了制造阴极的方法，其需要相对较少和有些简单的步骤。 新颖的蚀刻剂气体化学物质需要第二钝化层（PA2）。 没有单独的掩模形成直通通孔。 金属栅极（MG）的访问和隔离特征在与相关联的钝化层相同的图案化操作中被图案化，分配了对各自的单独图案化的需要。 蚀刻对硅氮化物具有高选择性。 消除了至少一个钝化层沉积，直接通孔掩模步骤和用于钝化层和金属栅极的分离的图案化步骤的要求。

    GRIPPING MULTI-LEVEL MATRIX STRUCTURE AND METHOD OF FORMATION THEREOF
    10.
    发明申请
    GRIPPING MULTI-LEVEL MATRIX STRUCTURE AND METHOD OF FORMATION THEREOF 审中-公开
    提取多层次矩阵结构及其形成方法

    公开(公告)号：WO0193298A8

    公开(公告)日：2007-11-01

    申请号：PCT/US0114897

    申请日：2001-05-09

    Applicant: CANDESCENT INTELLECTUAL PROP

    Inventor： PORTER JOHN D ,  MACKEY BOB L ,  NEIMEYER ROBERT G ,  SPINDT CHRISTOPHER J ,  CHANG DAVID C ,  SAHLSTROM KRIS E

    IPC: H01J9/227 ,  H01J29/02 ,  H01J29/32 ,  H01J29/86 ,  H01J29/87 ,  H01J31/12 ,  H01J9/18 ,  H01J29/18

    CPC classification number: H01J29/028 ,  H01J29/864 ,  H01J2329/00 ,  H01J2329/863

    Abstract: A multi-level matrix structure (100) for retaining a support structure within a flat panel display device. In one embodiment, the multi-level matrix structure (100) is comprised of first parallel ridges (102). The multi-level matrix structure (100) further includes second parallel ridges (104). The second parallel ridges (104) are oriented substantially orthogonally with respect to the first parallel ridges (102). In this embodiment, the second parallel ridges (104) have a height which is greater than the height of the first parallel ridges (102). Furthermore, in this embodiment, the second plurality of parallel spaced apart ridges (104) include contact portions (106) for retaining a support structure at a desired location within a flat panel display device. Hence, when a support structure is inserted between at least two of the contact portions (106) of the multi-level support structure (100), the support structure is retained in place, at a desired location within the flat panel display device, by the contact portions (106).

    Abstract translation: 一种用于将支撑结构保持在平板显示装置内的多级矩阵结构（100）。 在一个实施例中，多级矩阵结构（100）由第一平行脊（102）组成。 多级矩阵结构（100）还包括第二平行脊（104）。 第二平行脊（104）相对于第一平行脊（102）基本正交地定向。 在该实施例中，第二平行脊（104）的高度大于第一平行脊（102）的高度。 此外，在该实施例中，第二多个平行间隔开的​​脊（104）包括用于将支撑结构保持在平板显示装置内的期望位置处的接触部分（106）。 因此，当在多层支撑结构（100）的至少两个接触部分（106）之间插入支撑结构时，支撑结构被保持在平板显示装置内的所需位置的适当位置，由 接触部分（106）。

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