公开(公告)号：KR1020090120119A

公开(公告)日：2009-11-24

申请号：KR1020080046000

申请日：2008-05-19

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  한정욱 ,  유재민 ,  정영천 ,  박상훈 ,  노관종 ,  임병철 ,  정용석

IPC: H01L29/78

CPC classification number: H01L29/4234 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

Abstract: PURPOSE: A fine transistor and a method for manufacturing the same are provided to make a manufacturing process simple by forming a space through a round etching and forming a SONOS cell using a charge trap layer. CONSTITUTION: In a fine transistor and a method for manufacturing the same, a tunnel oxide film is formed on a semiconductor substrate(100). A nitride film and a passivation are formed on the tunnel oxide film(110), and the passivation is pattern and is used as a mask to etch the nitride film, and charge trapping layers(123) which are separated from each other. A blocking insulation film(124) is formed on a formed nitride film, and an electrode is formed on the blocking oxide film and the tunnel oxide film.

Abstract translation: 目的：提供精细晶体管及其制造方法，以通过圆形蚀刻形成空间并使用电荷陷阱层形成SONOS电池来简化制造工艺。 构成：在微细晶体管及其制造方法中，在半导体衬底（100）上形成隧道氧化膜。 在隧道氧化膜（110）上形成氮化物膜和钝化层，并且钝化是图案，并用作掩模以蚀刻氮化物膜，并对彼此分离的电荷俘获层（123）进行充电。 在形成的氮化物膜上形成阻挡绝缘膜（124），并且在阻挡氧化膜和隧道氧化物膜上形成电极。

公开(公告)号：KR1020090047774A

公开(公告)日：2009-05-13

申请号：KR1020070113795

申请日：2007-11-08

Applicant: 삼성전자주식회사

Inventor： 유태광 ,  한정욱 ,  김용태

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/28273 ,  H01L27/10891

Abstract: 비휘발성 메모리 소자 및 그 형성방법이 제공된다. 상기 비휘발성 메모리 소자는 반도체 기판에 활성 영역을 정의하며, 제 1 소자분리막과 제 2 소자분리막을 포함하는 소자분리막, 상기 활성 영역 및 상기 제 1 소자분리막을 가로지르는 워드 라인, 및 상기 활성 영역 및 상기 제 2 소자분리막을 가로지르는 센스 라인을 포함하되, 상기 제 1 소자분리막은 상기 활성 영역의 상부 측면을 노출하며, 상기 반도체 기판의 상기 활성 영역의 상부면보다 낮은 상부면을 가지며, 상기 제 2 소자분리막은 상기 반도체 기판의 상기 활성 영역의 상부면과 실질적으로 동일한 높이의 상부면을 가진다.
EEPROM, 셀 전류, 커플링 비

公开(公告)号：KR1020090018444A

公开(公告)日：2009-02-20

申请号：KR1020070082892

申请日：2007-08-17

Applicant: 삼성전자주식회사

Inventor： 이용규 ,  한정욱 ,  전희석

IPC: H01L27/115

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/2436

Abstract: A semiconductor device and a manufacturing method thereof are provided to minimize deterioration of a driving characteristic of a high voltage transistor by forming a high dielectric film with higher dielectric constant than a silicon oxide film. A semiconductor device(200) includes a semiconductor substrate(100), a nonvolatile memory element, a high voltage transistor, and a low voltage transistor. The semiconductor substrate includes a cell region, a high voltage region and a low voltage region. The nonvolatile memory element is arranged in the cell region. The high voltage transistor is arranged in the high voltage region. The high voltage transistor is driven by the first voltage. The low voltage transistor is arranged in the low voltage region. The low voltage transistor is driven by the lower voltage than the first voltage. The high voltage transistor includes a first high dielectric film(55) and a first gate electrode(60). The first high dielectric film is formed on the semiconductor substrate. The first gate electrode is formed on the first high dielectric layer.

Abstract translation: 提供半导体器件及其制造方法，通过形成比氧化硅膜高的介电常数的高电介质膜来最小化高电压晶体管的驱动特性的劣化。 半导体器件（200）包括半导体衬底（100），非易失性存储元件，高压晶体管和低压晶体管。 半导体衬底包括单元区域，高电压区域和低电压区域。 非易失性存储元件布置在单元区域中。 高压晶体管配置在高压区域。 高压晶体管由第一电压驱动。 低电压晶体管布置在低电压区域中。 低压晶体管由比第一电压低的电压驱动。 高压晶体管包括第一高介电膜（55）和第一栅电极（60）。 第一高电介质膜形成在半导体衬底上。 第一栅电极形成在第一高电介质层上。

公开(公告)号：KR1020080100649A

公开(公告)日：2008-11-19

申请号：KR1020070046615

申请日：2007-05-14

Applicant: 삼성전자주식회사

Inventor： 양승진 ,  한정욱 ,  김용태 ,  최용석 ,  권혁기

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L27/105 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The logic circuit and the memory circuit of different thickness of the gate insulating layer are formed on the different substrate. These substrates are laminated. The logic circuit and memory circuit are electrically connected through the through via. The semiconductor device(100) is provided. The semiconductor layer(101) including the first circuit having the gate insulating layer of the first thickness is formed on the first substrate(110). The second semiconductor layer(102) including second circuit having the gate insulating layer of the second thickness different from the first thickness is formed on the second substrate(150). The via(170) passes through a part of the first and the second semiconductor layer, and connects electrically the first and the second circuit.

Abstract translation: 栅极绝缘层的不同厚度的逻辑电路和存储电路形成在不同的衬底上。 层压这些基板。 逻辑电路和存储器电路通过通孔电连接。 提供半导体器件（100）。 包括具有第一厚度的栅极绝缘层的第一电路的半导体层（101）形成在第一基板（110）上。 在第二基板（150）上形成包括第二厚度不同于第一厚度的栅极绝缘层的第二电路的第二半导体层（102）。 通孔（170）穿过第一和第二半导体层的一部分，并且电连接第一和第二电路。

公开(公告)号：KR100854504B1

公开(公告)日：2008-08-26

申请号：KR1020070024126

申请日：2007-03-12

Applicant: 삼성전자주식회사

Inventor： 박원호 ,  한정욱 ,  김용태

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881 ,  H01L21/67069

Abstract: A method for fabricating a flash memory device is provided to form a floating gate whose width is decrease as it goes from its upper surface to its intermediate portion, by making a floating gate have a sharp upper corner without using a high temperature process. A first dielectric layer(105) is formed on an active region(103) of a semiconductor substrate(100). A first conductive layer is formed on the semiconductor substrate with the first dielectric layer. A mask pattern is formed on the first conductive layer. The first conductive layer is etched by using the mask pattern as an etch mask to form a first conductive pattern(110a) in which at least one portion of the first conductive pattern is decreased and increased in width. A second dielectric layer(125) is formed on the semiconductor substrate with the first conductive pattern. A second conductive pattern(130) is formed on the semiconductor substrate with the second dielectric layer, crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern. The process for forming the first conductive layer can include the following steps. An undeoped polysilicon layer is formed on the substrate with the first dielectric layer. First impurity ions are implanted into the undoped polysilicon layer by an ion implantation technique to form a silicon layer containing implanted atoms.

Abstract translation: 提供一种用于制造闪速存储器件的方法，以形成浮动栅极，其宽度随着其从上表面到其中间部分而减小，通过使漂浮栅极具有锐利的上角而不使用高温处理。 第一电介质层（105）形成在半导体衬底（100）的有源区（103）上。 在具有第一介电层的半导体衬底上形成第一导电层。 在第一导电层上形成掩模图案。 通过使用掩模图案作为蚀刻掩模来蚀刻第一导电层，以形成第一导电图案（110a），其中第一导电图案的至少一部分减小并且宽度增加。 在第一导电图案的半导体衬底上形成第二电介质层（125）。 第二导电图案（130）在具有第二介电层的半导体衬底上形成，与相邻于第一导电图案的有源区交叉并且部分地覆盖第一导电图案。 形成第一导电层的工艺可以包括以下步骤。 在具有第一介电层的基板上形成未形成的多晶硅层。 通过离子注入技术将第一杂质离子注入到未掺杂多晶硅层中以形成含有植入原子的硅层。

公开(公告)号：KR100842401B1

公开(公告)日：2008-07-01

申请号：KR1020060101256

申请日：2006-10-18

Applicant: 삼성전자주식회사

Inventor： 이용규 ,  한정욱 ,  전희석 ,  김영호 ,  천명조

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/7881 ,  H01L29/66825 ,  H01L21/28141

Abstract: A nonvolatile memory device and a method for fabricating the same are provided to prevent program errors by preventing a voltage drop between source/drain regions caused by a punch-through effect of a drain voltage. A semiconductor substrate(10) includes source/drain regions(12,15) are formed at both ends of a channel region. A gate structure(26) is separated at a predetermined interval from the source region in order to form an offset region. The gate structure includes a charge accumulation region(24) and a control gate(25). The charge accumulation region is overlapped partially with the drain region to be stacked on the channel region. A spacer is arranged at both sidewalls of the gate structure. A threshold value of the offset region is changed on the basis of a dielectric constant of the spacer.

Abstract translation: 提供非易失性存储器件及其制造方法，以通过防止由漏极电压的穿透效应引起的源极/漏极区域之间的电压降来防止程序错误。 半导体衬底（10）包括在沟道区域的两端形成源/漏区（12,15）。 为了形成偏移区域，栅极结构（26）以预定间隔从源极区域分离。 栅结构包括电荷累积区（24）和控制栅（25）。 电荷累积区域与要堆叠在沟道区域上的漏极区域部分地重叠。 间隔件布置在栅极结构的两个侧壁处。 基于间隔物的介电常数来改变偏移区域的阈值。

公开(公告)号：KR100830577B1

公开(公告)日：2008-05-22

申请号：KR1020060097469

申请日：2006-10-03

Applicant: 삼성전자주식회사

Inventor： 전희석 ,  한정욱

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/11253 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

Abstract: 마스크롬, 마스크롬 임베디드 이이피롬 및 이들의 제조 방법을 제공한다. 본 발명은 2-트랜지스터 이이피롬과 유사한 구조의 마스크롬을 제공한다. 이 마스크롬은 온 셀 및 오프 셀을 포함하고, 상기 온 셀 및 상기 오프 셀은 각각 선택 트랜지스터 및 메모리 트랜지스터를 포함한다. 상기 온 셀은 상기 선택 게이트 패턴과 상기 메모리 게이트 패턴 사이에 셀 확산 영역이 형성되고, 상기 오프 셀은 상기 선택 게이트 패턴과 상기 메모리 게이트 패턴 사이에 셀 확산 영역이 형성되지 않은 것이 특징이다. 이온주입 공정을 이용하여 셀 확산 영역을 형성하는 마스크를 변형함으로써 마스크롬 셀을 온 셀 및 오프 셀로 코딩할 수 있다. 따라서, 기존 마스크롬을 형성하는데 필요한 코딩용 마스크가 불필요하고, 제조 원가의 감소 및 제조 시간을 단축할 수 있다.
마스크롬, 이이피롬, 임베디드

公开(公告)号：KR1020070064905A

公开(公告)日：2007-06-22

申请号：KR1020050125499

申请日：2005-12-19

Applicant: 삼성전자주식회사

Inventor： 강상우 ,  한정욱 ,  박원호 ,  박성우

IPC: H01L27/115

Abstract: A method for fabricating an EEPROM is provided to reduce the width of an active region and a wordline by forming a tunnel insulation layer in a smaller area than an area that can be defined by a photolithography process. An isolation layer for defining an active region is formed in a semiconductor substrate(150), and a gate insulation layer(154), a hard mask layer and an ARC(anti-reflective coating) are sequentially formed on the active region. A first photoresist pattern is formed which has a first opening to which a part of the ARC is exposed. The first photoresist pattern is reflowed to reduce the width of the first opening. The ARC and the hard mask layer are etched by using the first photoresist pattern as an etch mask to form a second opening to which the gate insulation layer is exposed. The first photoresist pattern is removed. The gate insulation layer is isotropically wet-etched to form a tunneling opening by using the hard mask layer as an etch mask. The hard mask layer and the ARC are removed. A tunnel insulation layer(166) is formed in the tunneling opening. Impurities are implanted through the gate insulation layer exposed to the second opening.

Abstract translation: 提供了一种用于制造EEPROM的方法，通过在比通过光刻工艺限定的区域更小的区域中形成隧道绝缘层来减小有源区和字线的宽度。 在半导体衬底（150）中形成用于限定有源区的隔离层，并且在有源区上依次形成栅极绝缘层（154），硬掩模层和ARC（抗反射涂层）。 形成第一光致抗蚀剂图案，其具有暴露ARC的一部分的第一开口。 第一光致抗蚀剂图案被回流以减小第一开口的宽度。 通过使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻ARC和硬掩模层，以形成暴露栅极绝缘层的第二开口。 去除第一光致抗蚀剂图案。 栅极绝缘层通过使用硬掩模层作为蚀刻掩模进行各向同性地湿式蚀刻以形成隧道开口。 去除硬掩模层和ARC。 在隧道开口中形成隧道绝缘层（166）。 通过暴露于第二开口的栅绝缘层植入杂质。

公开(公告)号：KR100706789B1

公开(公告)日：2007-04-12

申请号：KR1020050110006

申请日：2005-11-17

Applicant: 삼성전자주식회사

Inventor： 서보영 ,  전희석 ,  한정욱 ,  강성택

IPC: H01L21/8247

公开(公告)号：KR100669347B1

公开(公告)日：2007-01-16

申请号：KR1020050109998

申请日：2005-11-17

Applicant: 삼성전자주식회사

Inventor： 전희석 ,  한정욱 ,  이창훈 ,  강성택

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  Y10S257/90 ,  H01L21/28273

Abstract: A semiconductor device and its forming method are provided to reduce remarkably the size of the semiconductor device by using a floating junction between a self aligned select element and a memory element. A semiconductor device includes a nonvolatile memory device(140) on a substrate(100), a first select device(142) at one side of the nonvolatile memory element on the substrate, and a floating junction. The floating junction(128) is formed between the nonvolatile memory device and the first select device in the substrate. The gate of the first select device is made of one conductive layer. The nonvolatile memory device is composed of a floating gate, a control gate and an insulating layer between the floating gate and the control gate.

Abstract translation: 提供一种半导体器件及其形成方法，通过使用自对准选择元件和存储元件之间的浮动结，显着地减小半导体器件的尺寸。 半导体器件包括在衬底（100）上的非易失性存储器件（140），在衬底上的非易失性存储元件的一侧的第一选择器件（142）和浮置结。 浮置接点（128）形成在非易失性存储器件和衬底中的第一选择器件之间。 第一选择装置的栅极由一个导电层制成。 非易失性存储器件由浮置栅极，控制栅极和浮置栅极与控制栅极之间的绝缘层构成。