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公开(公告)号：WO2022146109A1
公开(公告)日：2022-07-07
申请号：PCT/KR2021/095031
申请日：2021-01-25
Applicant: 한국과학기술원
Abstract: 본 발명은 깊이 이미지에서 적외선 이미지로의 도메인 전이학습을 기반으로 빠른 손 동작에 대한 3차원 손 자세를 추정하는 손 자세 추정 방법 및 시스템에 관한 것으로서, 손 움직임에 대한 깊이 이미지 및 적외선 이미지를 처리하는 단계, 손 이미지 생성기(HIG)를 이용하여 상기 적외선 이미지에서 깊이 맵을 합성하며, 상기 깊이 맵 및 적외선 맵 각각에서 손 관절의 골격 위치를 추정하는 단계 및 상기 골격 위치와 손 깊이 이미지의 중심을 이용하여 3차원 손 자세를 산출하는 단계를 포함한다.
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公开(公告)号：KR101815575B1
公开(公告)日：2018-01-05
申请号：KR1020150115851
申请日：2015-08-18
Applicant: 한국과학기술원
Abstract: 벽면반사에의한음파의지연시간을통한온도장측정방법및 시스템이제공된다. 본발명의실시예에따른온도장측정방법은, 음원에서발생된음파가제1 경로로수신되는데소요된제1 지연시간과음파가제2 경로로수신되는데소요된제2 지연시간을계산하고, 지연시간들을이용하여음원이배치된측정대상면의온도장을측정한다. 이에의해, 음원-센서개수의증가없이도추가적인입력정보를획득할수 있으므로일정수준이상의측정정확도확보가가능해진다.
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3.发明授权수직 구조를 갖는 독립적 및 대칭적인 이중 게이트 구조를 이용한 전자-정공 이중층 터널 전계 효과 트랜지스터 및 그 제조 방법 有权具有独立和对称双门的垂直结构化电子双层隧道场效应晶体管的建议和制造方法
公开(公告)号：KR101368191B1
公开(公告)日：2014-02-28
申请号：KR1020130000434
申请日：2013-01-03
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66666 , H01L29/66931 , H01L29/7827
Abstract: The present invention relates to an electronic-hole double layer tunnel field effect transistor, where a source region, a channel and a drain region are arranged at a substrate in a vertical direction, including a double gate structure. The present invention relates to the electronic-hole double layer tunnel field effect transistor and a manufacturing method thereof capable of increasing the degree of integration of the transistor at the substrate by having a vertical structure, being the electronic-hole double layer tunnel field effect transistor by applying different electrodes to the double gate structure, improving the inclination under threshold voltage and increasing operating current by using a double gate p-i-n structure and tunneling between bands, and having an implementable symmetrical double gate structure by proposing a gate of a symmetrical structure.
Abstract translation: 本发明涉及一种电子双层隧道场效应晶体管，其中源极区，沟道和漏极区在垂直方向的衬底上排列，包括双栅结构。 电子双层隧道场效应晶体管及其制造方法技术领域本发明涉及电子双层隧道场效应晶体管及其制造方法，该晶体管的制造方法能够通过具有垂直结构来提高晶体管在基板上的集成度，作为电子双层隧道场效应晶体管 通过对双栅极结构施加不同的电极，通过使用双栅极引脚结构和带之间的隧穿，提高阈值电压下的倾斜度和提高工作电流，并且通过提出对称结构的栅极具有可实现的对称双栅极结构。
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公开(公告)号：KR101367989B1
公开(公告)日：2014-02-28
申请号：KR1020120143638
申请日：2012-12-11
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L29/785
Abstract: The purpose of the present invention is to provide a transistor having improved performance than a conventional FinFET by manufacturing a UTFinFET having an ultra-thin fin (UTFin) whose thickness is thinner than that of a fin which can be manufactured by a conventional FinFET manufacturing process. In order to achieve the purpose, a semiconductor device according to the present invention comprises a step of forming two Si-UTFins which protrude from a substrate and are formed on both sides of a fin made of Si and SiGe layers using an epitaxy method. The UTFin formed in this method replaces the role of a fin of a conventional FinFET. A UTFin formed using an epitaxy method overcomes a thickness limit which a fin formed by lithography has, and can have a thickness of less than 10 nm. [Reference numerals] (AA) Step of preparing a Si substrate; (BB) Step of forming a SiGe layer; (CC) Step of placing a hard mask on a Si-Fin area by patterning the hard mask on the SiGe layer; (DD) Step of forming a Si-Fin through an etching process; (EE) Step of growing a Si layer on both sides of the Si-Fin and both sides of the SiGe layer in an epitaxy method; (FF) Step of forming a first impurity resign by firstly doping an impurity into a Si-UTFin; (GG) Step of etching the hard mask; (HH) Step of firstly depositing oxide in a region etched while forming the Si-Fin, making an oxide surface even, and etching the oxide; (II) Step of forming two Si-UTFins on both sides of the Si-Fin and both sides of the SiGe layer; (JJ) Step of forming an air filled structure in a space formed by a secondly deposited oxide, the lower part of the Si-UTFin, and the Si-Fin by secondly depositing oxide onto inner walls, outer walls, top between two Si-UTFins under poor step coverage conditions and making an oxide surface even; (KK) Step of depositing a gate stack electrode; (LL) Step of forming source and drain regions which are second and third impurity regions respectively by secondly and thirdly doping on left and right sides of the Si-UTFin
Abstract translation: 本发明的目的是通过制造具有厚度比通过常规FinFET制造工艺制造的鳍片厚度的超薄鳍片（UTFin）的UTFinFET来提供具有比常规FinFET具有改进的性能的晶体管 。 为了实现这一目的，本发明的半导体器件包括从基板突出并且使用外延法在由Si和SiGe层制成的鳍的两侧上形成两个Si-UTFin的步骤。 以该方法形成的UTFin替代了常规FinFET鳍片的作用。 使用外延法形成的UTFin克服了通过光刻形成的翅片的厚度限制，并且可以具有小于10nm的厚度。 （附图标记）（AA）制备Si衬底的步骤; （BB）形成SiGe层的工序; （CC）通过在SiGe层上构图硬掩模，将硬掩模放置在Si-Fin区域上的步骤; （DD）通过蚀刻工艺形成Si-Fin的步骤; （EE）在外延法中在Si-Fin两面和SiGe层的两面上生长Si层的步骤; （FF）通过首先将杂质掺杂到Si-UTFin中来形成第一杂质的步骤; （GG）蚀刻硬掩模的步骤; （HH）在形成Si-Fin的同时蚀刻的区域中首先沉积氧化物，使氧化物表面均匀并蚀刻氧化物的步骤; （II）在Si-Fin两面和SiGe层的两侧形成两个Si-UTFin的步骤; （JJ）在由二次沉积的氧化物形成的空间中形成充气结构的步骤，Si-UTFin的下部和通过将氧化物二次沉积到内壁，外壁，两个Si- UTFins在较差的步骤覆盖条件下，使氧化物表面均匀; （KK）沉积栅堆叠电极的步骤; （LL）通过在Si-UTFin的左侧和右侧二次和三次掺杂而分别形成第二和第三杂质区的源区和漏区的步骤
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公开(公告)号：KR102211021B1
公开(公告)日：2021-02-02
申请号：KR1020190008361
申请日：2019-01-22
Applicant: 한국과학기술원
Abstract: 웹콘텐츠의일관성결정장치로서, 웹콘텐츠의제목및 본문을수신하면, 상기제목을임베딩하여제목임베딩벡터를생성하고, 상기본문에포함된적어도하나이상의문단들을각각임베딩하여본문문단임베딩벡터를각 문단들별로생성하는임베딩벡터생성부, 그리고상기제목임베딩벡터및 상기본문문단임베딩벡터를순환신경망모델(Recurrent Neural Network Model)에입력하여적어도하나이상의은닉상태값들을결정하고, 상기은닉상태값들을이용하여상기제목과상기본문의일관성점수를결정하는일관성결정부를포함한다.
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Patent Agency Ranking
公开(公告)号：KR101367988B1
公开(公告)日：2014-02-28
申请号：KR1020120142808
申请日：2012-12-10
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L29/785
Abstract: The purpose of the present invention is to provide a transistor having improved performance than a conventional FinFET by manufacturing a UTFinFET having an ultra-thin fin (UTFin) whose thickness is thinner than that of a fin which can be manufactured by a conventional FinFET manufacturing process. In order to achieve the purpose, a semiconductor device according to the present invention comprises a step of forming two Si-UTFins which protrude from a substrate and are formed on both sides of a fin made of Si and SiGe layers using an epitaxy method. The UTFin formed in this method replaces the role of a fin of a conventional FinFET. A UTFin formed using an epitaxy method overcomes a thickness limit which a fin formed by lithography has, and can have a thickness of less than 10 nm. [Reference numerals] (AA) Step of preparing a Si substrate; (BB) Step of forming a SiGe layer; (CC) Step of placing a hard mask on a Si-Fin area by patterning the hard mask on the SiGe layer; (DD) Step of forming a Si-Fin through an etching process; (EE) Step of growing a Si layer on both sides of the Si-Fin and both sides of the SiGe layer in an epitaxy method; (FF) Step of forming a first impurity doped resign by firstly doping an impurity into a Si-UTFin; (GG) Step of etching the hard mask; (HH) Step of firstly depositing oxide in a region etched while forming the Si-Fin, making an oxide surface even, and etching the oxide; (II) Step of forming two Si-UTFins on both sides of the Si-Fin and both sides of the SiGe layer; (JJ) Step of forming an intermediate dielectric layer by filling dielectric material between two Si-UTFins; (KK) Step of leaving the intermediate dielectric layer between two Si-UTFins and removing the intermediate dielectric layer on outer walls of two Si-UTFins through an etching process; (LL) Step of secondly depositing oxide on the outer walls of two Si-UTFins and the intermediate dielectric layer and making an oxide surface even; (MM) Step of depositing a gate stack electrode; (NN) Step of forming source and drain regions which are second and third impurity regions respectively by secondly and thirdly doping on left and right sides of the Si-UTFin
Abstract translation: 本发明的目的是通过制造具有厚度比通过常规FinFET制造工艺制造的鳍片厚度的超薄鳍片（UTFin）的UTFinFET来提供具有比常规FinFET具有改进的性能的晶体管 。 为了实现这一目的，本发明的半导体器件包括从基板突出并且使用外延法在由Si和SiGe层制成的鳍的两侧上形成两个Si-UTFin的步骤。 以该方法形成的UTFin替代了常规FinFET鳍片的作用。 使用外延法形成的UTFin克服了通过光刻形成的翅片的厚度限制，并且可以具有小于10nm的厚度。 （附图标记）（AA）制备Si衬底的步骤; （BB）形成SiGe层的步骤; （CC）通过在SiGe层上构图硬掩模，将硬掩模放置在Si-Fin区域上的步骤; （DD）通过蚀刻工艺形成Si-Fin的步骤; （EE）在外延法中在Si-Fin两面和SiGe层的两面上生长Si层的步骤; （FF）通过首先将杂质掺杂到Si-UTFin中形成第一杂质掺杂的步骤; （GG）蚀刻硬掩模的步骤; （HH）在形成Si-Fin的同时蚀刻的区域中首先沉积氧化物，使氧化物表面均匀并蚀刻氧化物的步骤; （II）在Si-Fin两面和SiGe层的两侧形成两个Si-UTFin的步骤; （JJ）通过在两个Si-UTF之间填充介电材料形成中间介电层的步骤; （KK）通过蚀刻工艺在两个Si-UTFins之间离开中间介电层并去除两个Si-UTFin的外壁上的中间介电层; （LL）在两个Si-UTFin和中间介电层的外壁上二次沉积氧化物并使氧化物表面均匀的步骤; （MM）沉积栅堆叠电极的步骤; （NN）通过在Si-UTFin的左侧和右侧二次和三次掺杂而分别形成第二和第三杂质区的源区和漏区的步骤
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公开(公告)号：KR1020130063691A
公开(公告)日：2013-06-17
申请号：KR1020110130189
申请日：2011-12-07
Applicant: 한국과학기술원
Abstract: PURPOSE: A tunnel structure for reducing micro pressure wave in a tunnel is provided to reduce pressure wave and micro pressure wave generated due to the progress of a vehicle. CONSTITUTION: A tunnel structure for reducing micro pressure wave in a tunnel comprises a tunnel wall(20) and a pressure wave reduction module(40). The tunnel wall is formed with a tunnel(10) inside to pass a high speed train. The pressure wave reduction module comprises a pressure wave reduction pipe(42) and a plunger(44). The pressure wave reduction pipe is connected to the tunnel and is lengthily extended in the longitudinal direction of the tunnel wall. The plunger is arranged inside the pressure wave reduction pipe. The plunger longitudinally moves inside the pressure wave reduction pipe.
Abstract translation: 目的：提供一种用于减小隧道中微压波的隧道结构，以减少由于车辆进展而产生的压力波和微压波。 构成：用于减少隧道中的微压波的隧道结构包括隧道壁（20）和压力波减少模块（40）。 隧道壁内部设有通道（10），以通过高速列车。 压力波减少模块包括压力波减压管（42）和柱塞（44）。 压力波减压管连接到隧道，并沿隧道壁的纵向方向延伸。 柱塞布置在压力波减压管内。 柱塞在压力波减压管内纵向移动。
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公开(公告)号：KR1020170084892A
公开(公告)日：2017-07-21
申请号：KR1020160004289
申请日：2016-01-13
Applicant: 한국과학기술원
Abstract: 사용자에게착용된단일깊이카메라에의해촬영되는손의제 1 시퀀스영상을획득하는단계; 획득한제 1 시퀀스영상내 복수의프레임으로부터제 1 시공간특징벡터(spatio-temporal feature vector)를획득하는단계; 클릭동작의발생여부및 클릭위치에대한정보를알고있는손의제 2 시퀀스영상의프레임으로부터추출된제 2 시공간특징벡터에기초하여, 랜덤포레스트(random forest)를구성하는단계; 및제 1 시공간특징벡터를랜덤포레스트에입력하여, 제 1 시퀀스영상에서손의클릭동작의발생여부및 클릭위치를판단하는단계를포함하는것을특징으로하는, 본발명의일 실시예에따른클릭감지장치에의한클릭감지방법이개시된다.
Abstract translation: 获取由用户佩戴的单个深度相机拍摄的手部的第一序列图像; 从获取的第一序列图像中的多个帧中获取第一时空特征向量; 基于从知道关于点击动作和点击位置的发生的信息的手的第二序列图像的帧中提取的第二时空特征向量构建随机森林; 并且将第一时空特征向量输入到随机森林，以确定在第一序列图像和点击位置中是否出现手的点击操作。根据本发明的实施例， 公开了一种检测点击的方法。
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公开(公告)号：KR101370244B1
公开(公告)日：2014-03-06
申请号：KR1020120114607
申请日：2012-10-16
Applicant: 한국과학기술원
CPC classification number: H04L63/1458 , H04L2463/142
Abstract: The present invention relates to a method for detecting and blocking distributed denial of service (DDos) evolved from an application layer DDoS attack and a device for the same. The method for detecting and blocking the application layer DDoS attack comprises the steps of: transmitting a link address of a web page to a client after modification and obfuscation; determining reliability by comparing a link address that the client accesses and the link address transmitted to the client; setting a reference value as a reference for blocking access to the web page, and deciding whether to block access to the web page of the client by comparing the reliability and the reference value. [Reference numerals] (110) Whether a server is overloaded?; (111) Change a link address of a web page transmitted based on each client information; (112) Obfuscate the changed link address; (113) Waiting for connection after transmitting the changed link address to a client; (120) Client access link address is the changed link address?; (121) Negative points on client's reliability; (122) Plus points on the client's reliability; (130) Reliability
Abstract translation: 本发明涉及一种用于检测和阻止从应用层DDoS攻击演变而来的分布式拒绝服务（DDos）及其设备的方法。 用于检测和阻止应用层DDoS攻击的方法包括以下步骤：在修改和混淆之后向客户端发送网页的链接地址; 通过比较客户端访问的链路地址和发送给客户端的链路地址来确定可靠性; 将参考值设置为阻止对网页的访问的参考，并且通过比较可靠性和参考值来决定是否阻止对客户端的网页的访问。 （附图标记）（110）服务器是否过载？ （111）根据每个客户端信息更改发送的网页的链接地址; （112）模糊变更的链接地址; （113）在将更改的链路地址发送给客户端之后等待连接; （120）客户端访问链接地址是更改后的链接地址？ （121）客户可靠性的负面点; （122）加点客户的可靠性; （130）可靠性<参考值 （131）阻止相应的客户端; （AA）开始
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公开(公告)号：KR101358906B1
公开(公告)日：2014-02-06
申请号：KR1020110130189
申请日：2011-12-07
Applicant: 한국과학기술원
Abstract: 본 발명에 따른 열차가 통과되는 터널구조에 있어서, 열차가 지나갈 수 있도록 내부에 터널(10)이 형성된 터널벽(20); 상기 터널(10)과 연통되고 상기 터널벽(20) 내부로 연장되어 형성되며, 저감시키고자 하는 압력파의 1/4 파장 길이로 형성된 압력파저감모듈(40)을 포함하고, 상기 압력파저감모듈(40)은 상기 터널(10)과 연통되어 상기 터널벽(20)의 길이방향으로 길게 연장되어 형성된 압력파저감관(42); 상기 압력파저감관(32)을 따라 이동되게 구성되어 상기 압력파저감관(32) 내부의 길이를 조절시키는 플런저(44)를 포함하기 때문에, 터널(10) 내부에서 발생되는 압력파 및 미기압파를 효과적으로 저감할 수 있고, 이를 통해 승객 귀에서 느끼는 압박감 및 터널 출입구 주변에서의 충격성 환경 압력파를 저감시키는 효과가 있다.
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